Combinatorial Logic

16.2.1.1 AND2

2-Input AND.

Figure 16-73. AND2

Table 16-165. AND2 I/O
Inputs	Output
A, B	Y

Table 16-166. AND2 Truth Table
A	B	Y
X	0	0
0	X	0
1	1	1

16.2.1.2 AND3

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3-Input AND.

Figure 16-74. AND3

Table 16-167. AND3 I/O
Input	Output
A, B, C	Y

Table 16-168. AND3 Truth Table
A	B	C	Y
X	X	0	0
X	0	X	0
0	X	X	0
1	1	1	1

16.2.1.3 AND4

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4-Input AND.

Figure 16-75. AND4

Table 16-169. AND4 I/O
Input	Output
A, B, C, D	Y

Table 16-170. AND4 Truth Table
A	B	C	D	Y
X	X	X	0	0
X	X	0	X	0
X	0	X	X	0
0	X	X	X	0
1	1	1	1	1

16.2.1.4 ARI1

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The ARI1 macro is responsible for representing all arithmetic operations in the pre-layout phase.

Figure 16-76. ARI1

Table 16-171. ARI1 I/O
Input	Output
A, B, C, D, FCI	Y, S, FCO

The ARI1 cell has a 20 bit INIT string parameter that is used to configure its functionality. The interpretation of the 16 LSB of the INIT string is shown in the following table. F0 is the value of Y when A = 0 and F1 is the value of Y when A = 1.

Table 16-172. Interpretation of 16 LSB of the INIT String for ARI1
ADCB	Y
0000	INIT[0]	F0
0001	INIT[1]
0010	INIT[2]
0011	INIT[3]
0100	INIT[4]
0101	INIT[5]
0110	INIT[6]
0111	INIT[7]
1000	INIT[8]	F1
1001	INIT[9]
1010	INIT[10]
1011	INIT[11]
1100	INIT[12]
1101	INIT[13]
1110	INIT[14]
1111	INIT[15]

Table 16-173. ARI1 Truth Table for S
Y	FCI	S
0	0	0
0	1	1
1	0	1
1	1	0

ARI1 LOGIC

The 4 MSB of the INIT string controls the output of the carry bits. The carry is generated using carry propagation and generation bits, which are evaluated according to the following tables.

Table 16-174. ARI1 INIT[17:16] String Interpretation
INIT[17]	INIT[16]	G
0	0	0
0	1	F0
1	0	1
1	1	F1

Table 16-175. ARI1 INIT[19:18] String Interpretation
INIT[19]	INIT[18]	P
0	0	0
0	1	Y
1	X	1

Table 16-176. FCO Truth Table
P	G	FCI	FCO
0	G	X	G
1	X	FCI	FCI

16.2.1.5 ARI1_CC

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The ARI1_CC macro is responsible for representing all arithmetic operations in the post-layout phase. It performs all the functions of the ARI1 maco except that it does not generate the Final Carry Out (FCO).

Note: FC1 and FC0 do not perform any functions.

Figure 16-77. ARI1_CC

Table 16-177. ARI1_CC I/O
Input	Output
A, B, C, D,CC	Y, S, P, UB

The ARI1_CC cell has a 20-bit INIT string parameter that is used to configure its functionality. The interpretation of  the 16 LSB of the INIT string is shown in the following table. F0 is the value of Y when A = 0 and F1 is the value of Y  when A = 1.

Table 16-178. INTERPRETATION OF 16 LSB OF THE INIT STRING FOR ARI1_CC
ADCB	Y
0000	INIT[0]	F0
0001	INIT[1]
0010	INIT[2]
0011	INIT[3]
0100	INIT[4]
0101	INIT[5]
0110	INIT[6]
0111	INIT[7]
1000	INIT[8]	F1
1001	INIT[9]
1010	INIT[10]
1011	INIT[11]
1100	INIT[12]
1101	INIT[13]
1110	INIT[14]
1111	INIT[15]

The 4 MSB of the INIT string controls the output of the carry bits. The carry is generated using carry propagation and generation bits, which are evaluated according to the following tables.

Table 16-179. ARI1_CC INIT[17:16] STRING INTERPRETATION
INIT[17]	INIT[16]	UB
0	0	1
0	1	!F0
1	0	0
1	1	!F1

Table 16-180. ARI1_CC INIT[19:18] STRING INTERPRETATION
INIT[19]	INIT[18]	P
0	0	0
0	1	Y
1	X	1

The equation of S is given by:

S = Y^CC

16.2.1.6 BUFD

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Buffer.

Note: The compile optimization does not remove this macro.

Figure 16-78 16-79. BUFD

Table 16-181 16-183. BUFD I/O
Input	Output
A	Y

Table 16-182 16-184. BUFD Truth Table
A	Y
0	0
1	1

16.2.1.7 BUFF

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Buffer.

Figure 16-78 16-79. BUFF

Table 16-181 16-183. BUFF I/O
Input	Output
A	Y

Table 16-182 16-184. BUFF Truth Table
A	Y
0	0
1	1

16.2.1.8 CFG1/2/3/4 and Look-Up Tables (LUTs)

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CFG1, CFG2, CFG3, and CFG4 are post-layout LUTs that implement any 1-input, 2-input, 3-input, and 4-input combinational logic functions respectively. Each of the CFG1/2/3/4 macros has an INIT string parameter that determines the logic functions of the macro. The output Y is dependent on the INIT string parameter and the values of the inputs.

16.2.1.9 CFG2

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Post-layout macro implements any 2-input combinational logic function. Output Y is dependent on the INIT string parameter and the value of A and B. The INIT string parameter is 4 bits wide.

Figure 16-80. CFG2

Table 16-185. CFG2 I/O
Input	Output
A,B	Y = f (INIT, A, B)

Table 16-186. CFG2 INIT String Interpretation
BA	Y
00	INIT[0]
01	INIT[1]
10	INIT[2]
11	INIT[3]

16.2.1.10 CFG3

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Post-layout macro used to implement any 3-input combinational logic function. Output Y is dependent on the INIT string parameter and the value of A, B, and C. The INIT string parameter is 8 bits wide.

Figure 16-81. CFG3

Table 16-187. CFG3 I/O
Input	Output
A, B, C	Y = f (INIT, A,B, C)

Table 16-188. CFG3 INIT String Interpretation
CBA	Y
000	INIT[0]
001	INIT[1]
010	INIT[2]
011	INIT[3]
100	INIT[4]
101	INIT[5]
110	INIT[6]
111	INIT[7]

16.2.1.11 CFG4

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Post-layout macro used to implement any 4-input combinational logic function. Output Y is dependent on the INIT string parameter and the value of A, B, C, and D. The INIT string parameter is 16 bits wide.

Figure 16-82. CFG4

Table 16-189. CFG4 I/O
Input	Output
A, B, C, D	Y = f (INIT, A,B, C, D)

Table 16-190. CFG4 Truth Table
DCBA	Y
0000	INIT[0]
0001	INIT[1]
0010	INIT[2]
0011	INIT[3]
0100	INIT[4]
0101	INIT[5]
0110	INIT[6]
0111	INIT[7]
1000	INIT[8]
1001	INIT[9]
1010	INIT[10]
1011	INIT[11]
1100	INIT[12]
1101	INIT[13]
1110	INIT[14]
1111	INIT[15]

16.2.1.12 INV

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Inverter.

Figure 16-83. INV

Table 16-191. INV I/O
Input	Output
A	Y

Table 16-192. INV Truth Table
A	Y
0	1
1	0

16.2.1.13 INVD

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Inverter.

Note: Compile optimization does not remove this macro.

Figure 16-84. INVD

Table 16-193. INVD I/O
Input	Output
A	Y

Table 16-194. INVD Truth Table
A	Y
0	1
1	0

16.2.1.14 MX2

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2 to 1 Multiplexer.

Figure 16-85. MX2

Table 16-195. MX2 I/O
Input	Output
A, B, S	Y

Table 16-196. MX2 Truth Table
A	B	S	Y
A	X	0	A
X	B	1	B

16.2.1.15 MX4

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4 to 1 Multiplexer.

This macro uses two logic modules.

Figure 16-86. MX4

Table 16-197. MX4 I/O
Input	Output
D0, D1, D2, D3, S0, S1	Y

Table 16-198. MX4 Truth Table
D3	D2	D1	D0	S1	S0	Y
X	X	X	D0	0	0	D0
X	X	D1	X	0	1	D1
X	D2	X	X	1	0	D2
D3	X	X	X	1	1	D3

16.2.1.16 NAND2

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2-Input NAND.

Figure 16-87. NAND2

Table 16-199. NAND2 I/O
Input	Output
A, B	Y

Table 16-200. NAND2 Truth Table
A	B	Y
X	0	1
0	X	1
1	1	0

16.2.1.17 NAND3

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3-Input NAND.

Figure 16-88. NAND3

Table 16-201. NAND3 I/O
Input	Output
A, B, C	Y

Table 16-202. NAND3 Truth Table
A	B	C	Y
X	X	0	1
X	0	X	1
0	X	X	1
1	1	1	0

16.2.1.18 NAND4

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4-input NAND.

Figure 16-89. NAND4

Table 16-203. NAND4 I/O
Input	Output
A, B, C, D	Y

Table 16-204. NAND4 Truth Table
A	B	C	D	Y
X	X	X	0	1
X	X	0	X	1
X	0	X	X	1
0	X	X	X	1
1	1	1	1	0

16.2.1.19 NOR2

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2-input NOR.

Figure 16-90. NOR2

Table 16-205. NOR2 I/O
Input	Output
A, B	Y

Table 16-206. NOR2 Truth Table
A	B	Y
0	0	1
X	1	0
1	X	0

16.2.1.20 NOR3

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3-input NOR.

Figure 16-91. NOR3

Table 16-207. NOR3 I/O
Input	Output
A, B, C	Y

Table 16-208. NOR3 Truth Table
A	B	C	Y
0	0	0	1
X	X	1	0
X	1	X	0
1	X	X	0

16.2.1.21 NOR4

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4-input NOR.

Figure 16-92. NOR3

Table 16-209. NOR4 I/O
Input	Output
A, B, C, D	Y

Table 16-210. NOR4 Truth Table
A	B	C	D	Y
0	0	0	0	1
1	X	X	X	0
X	1	X	X	0
X	X	1	X	0
X	X	X	1	0

16.2.1.22 OR2

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2-input OR.

Figure 16-93. OR2

Table 16-211. OR2 I/O
Input	Output
A, B	Y

Table 16-212. OR2 Truth Table
A	B	Y
0	0	0
X	1	1
1	X	1

16.2.1.23 OR3

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3-input OR.

Figure 16-94. OR3

Table 16-213. OR3 I/O
Input	Output
A, B, C	Y

Table 16-214. OR3 Truth Table
A	B	C	Y
0	0	0	0
X	X	1	1
X	1	X	1
1	X	X	1

16.2.1.24 OR4

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4-input OR.

Figure 16-95. OR4

Table 16-215. OR4 I/O
Input	Output
A, B, C, D	Y

Table 16-216. OR4 Truth Table
A	B	C	D	Y
0	0	0	0	0
1	X	X	X	1
X	1	X	X	1
X	X	1	X	1
X	X	X	1	1

16.2.1.25 XOR2

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2-input XOR.

Figure 16-96. XOR2

Table 16-217. XOR2 I/O
Input	Output
A, B	Y

Table 16-218. XOR2 Truth Table
A	B	Y
0	0	0
0	1	1
1	0	1
1	1	0

16.2.1.26 XOR3

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3-input XOR.

Table 16-219. XOR3 I/O
Input	Output
A, B, C	Y

Table 16-220. XOR3 Truth Table
A	B	C	Y
0	0	0	0
1	0	0	1
0	1	0	1
1	1	0	0
0	0	1	1
1	0	1	0
0	1	1	0
1	1	1	1

16.2.1.27 XOR4

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4-input XOR.

Table 16-221. XOR4 I/O
Input	Output
A, B, C, D	Y

Table 16-222. XOR4 Truth Table
A	B	C	D	Y
0	0	0	0	0
0	0	0	1	1
0	0	1	0	1
0	0	1	1	0
0	1	0	0	1
0	1	0	1	0
0	1	1	0	0
0	1	1	1	1
1	0	0	0	1
1	0	0	1	0
1	0	1	0	0
1	0	1	1	1
1	1	0	0	0
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0

16.2.1.28 XOR8

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8-input XOR.

This macro uses two logic modules.

Table 16-223. XOR8 I/O
Input	Output
A, B, C, D, E, F, G, H	Y

If you have an odd number of inputs that are High, the output is High (1).

If you have an even number of inputs that are High, the output is Low (0).

For example:

Table 16-224. XOR8 Truth Table
G	H	Y
0	0	0
0	1	1
1	1	0

16.2.1.29 LIVE_PROBE_FB

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This is a special-purpose macro that feeds the live probe signals back to the fabric. You can connect the PROBE_A/PROBE_B signals to any unused I/O during design generation. This is useful if PROBE_A/PROBE_B cannot be brought out for debugging due to board limitations. PROBE_A and PROBE_B pins must be reserved, if LIVE_PROBE_FB macro is used. This macro is not supported in simulation.