10.2 Introduction

In the FPGA design world, constraint files are as important as design source files. Physical Design Constraints (PDC) are used to constrain the I/O attributes, placement, and routing during the physical layout phase.

You can enter PDC commands manually using the Libero^® SoC Text Editor. PDC commands can also be generated using Libero SoC’s interactive tools. The I/O Attribute Editor is the interactive tool for making I/O attribute changes, and the Chip Planner is the interactive tool for making floorplanning changes.

When changes are made in the I/O Attribute Editor or the Chip Planner, the PDC file(s) are updated to reflect the changes. These PDC commands can be used as part of a script file to constrain the Place and Route step of your design.