16.2.2 Sequential Logic
(Ask a Question)16.2.2.1 DFN1
(Ask a Question)D-Type Flip-Flop.Figure 16-101. DFN1 
| Input | Output |
|---|---|
| D, CLK | Q |
| CLK | D | Qn+1 |
|---|---|---|
| not Rising | X | Qn |
| — | D | D |
16.2.2.2 DFN1C0
(Ask a Question)D-Type Flip-Flop with active-low Clear.Figure 16-102. DFN1C0 
| Input | Output |
|---|---|
| D, CLK, CLR | Q |
| CLR | CLK | D | Qn+1 |
|---|---|---|---|
| 0 | X | X | 0 |
| 1 | not Rising | X | Qn |
| 1 | — | D | D |
16.2.2.3 DFN1E1
(Ask a Question)D-Type Flip-Flop with active high Enable.
Figure 16-103. DFN1E1
| Input | Output |
|---|---|
| D, E, CLK | Q |
| E | CLK | D | Qn+1 |
|---|---|---|---|
| 0 | X | X | Qn |
| 1 | not Rising | X | Qn |
| 1 | — | D | D |
16.2.2.4 DFN1E1C0
(Ask a Question)D-Type Flip-Flop, with active-high Enable and active-low Clear.Figure 16-104. DFN1E1C0 
| Input | Output |
|---|---|
| CLR, D, E, CLK | Q |
| CLR | E | CLK | D | Qn+1 |
|---|---|---|---|---|
| 0 | X | X | X | 0 |
| 1 | 0 | X | X | Qn |
| 1 | 1 | not Rising | X | Qn |
| 1 | 1 | — | D | D |
16.2.2.5 DFN1E1P0
(Ask a Question)D-Type Flip-Flop with active-high Enable and active-low Preset.Figure 16-105. DFN1E1P0 
| Input | Output |
|---|---|
| D, E, PRE, CLK | Q |
| PRE | E | CLK | D | Qn+1 |
|---|---|---|---|---|
| 0 | X | X | X | 1 |
| 1 | 0 | X | X | Qn |
| 1 | 1 | not Rising | X | Qn |
| 1 | 1 | — | D | D |
16.2.2.6 DLN1
(Ask a Question)Data Latch.
Figure 16-106. DLN1
| Input | Output |
|---|---|
| D, G | Q |
| G | D | Q |
|---|---|---|
| 0 | X | Q |
| 1 | D | D |
16.2.2.7 DLN1C0
(Ask a Question)Data Latch with active-low Clear.Figure 16-107. DLN1C0 
| Input | Output |
|---|---|
| CLR, D, G | Q |
| CLR | G | D | Q |
|---|---|---|---|
| 0 | X | X | 0 |
| 1 | 0 | X | Q |
| 1 | 1 | D | D |
16.2.2.8 DLN1P0
(Ask a Question)Data Latch with active-low Preset.Figure 16-108. DLN1P0 
| Input | Output |
|---|---|
| D, G, PRE | Q |
| PRE | G | D | Q |
|---|---|---|---|
| 0 | X | X | 1 |
| 1 | 0 | X | Q |
| 1 | 1 | D | D |
16.2.2.9 SLE
(Ask a Question)Sequential Logic Element.Figure 16-109. SLE 
| Input | Output | |
|---|---|---|
| Name | Function | Q |
| D | Data input | |
| CLK | Clock input | |
| EN | Active-High CLK enable | |
| ALn | Asynchronous Load. This active-Low signal either sets the register or clears the register depending on the value of ADn. | |
| ADn1 | Static asynchronous load data. When ALn is active, Q goes to the complement of ADn. | |
| SLn | Synchronous load. This active-Low signal either sets the register or clears the register depending on the value of SD, at the rising edge of clock. | |
| SD1 | Static synchronous load data. When SLn is active (that is, low), Q goes to the value of SD at the rising edge of CLK. | |
| LAT1 | Active-High Latch Enable. This signal enables latch mode when high and register mode when low. | |
- ADn, SD, and LAT are static signals defined at design time and need to be tied to 0 or 1.
| ALn | ADn | LAT | CLK | EN | SLn | SD | D | Qn+1 |
|---|---|---|---|---|---|---|---|---|
| 0 | ADn | X | X | X | X | X | X | !ADn |
| 1 | X | 0 | Not rising | X | X | X | X | Qn |
| 1 | X | 0 | — | 0 | X | X | X | Qn |
| 1 | X | 0 | — | 1 | 0 | SD | X | SD |
| 1 | X | 0 | — | 1 | 1 | X | D | D |
| 1 | X | 1 | 0 | X | X | X | X | Qn |
| 1 | X | 1 | 1 | 0 | X | X | X | Qn |
| 1 | X | 1 | 1 | 1 | 0 | SD | X | SD |
| 1 | X | 1 | 1 | 1 | 1 | X | D | D |