1.1 Libero SoC Design Suite v2024.2 Welcome Page

The Libero® System-on-chip (SoC) Design Suite offers high productivity with its comprehensive, easy-to-learn, easy-to-adopt development tools for designing with PolarFire®SoC, PolarFire®, IGLOO® 2, SmartFusion® 2, and RTG4™ families of FPGAs. The suite integrates industry-leading tools to enable customers to bring their Microchip FPGA based designs to market quickly and efficiently. The tool chain provides advanced synthesis, place and route, and simulation coupled with programming and debugging tools, and secure production programming support.

Important: For more information, see the Libero SoC Design Suite Release Notes.

What's New in Libero SoC Design Suite v2024.2

Changes That Address Important Issues

SmartFusion 2 and IGLOO 2

  • TAMPER: Remove Zeroize 'Recoverable' option

New Device Support

RT PolarFire SoC FPGA

  • Introduce RTPFS160ZT/TS/TL/TLS FCVG784 MIL STD 1.0V/1.05V Preliminary Timing & Power
  • Introduce RTPFS160ZT/TS FCVG784 MIL -1 1.0V/1.05V Preliminary Timing & Power
  • Introduce RTPFS460ZT/TS/TL/TLS CG1509 MIL STD 1.0V/1.05V Preliminary Timing & Power
  • Introduce RTPFS460ZT/TS CG1509 MIL -1 1.0V/1.05V Preliminary Timing & Power

PolarFire SoC

  • MPFS460T/TS/TL/TLS STD EXT/IND 1.0V/1.05V Production Timing and Power
  • MPFS460T/TS -1 EXT/IND 1.0V/1.05V Production Timing and Power
  • MPFS025T STD/-1 Automotive Tgrade2 Production Timing and Power
  • MPFS095T STD/-1 Automotive Tgrade2 Production Timing and Power
  • MPFS160T STD/-1 Automotive Tgrade2 Production Timing and Power
  • MPFS250T STD/-1 Automotive Tgrade2 Production Timing and Power

Software Features and Enhancements

  • Added static timing analysis option to ignore_clock_latency in set_max_delay and set_min_delay constraints. This could be applied to CDC paths while excluding clock path delay, clock skew, and clock jitter.
  • RTG4, PolarFire, PolarFire SoC: Synplify Pro added syn_fsm_correction directive to build single-bit error correction logic with Hamming distance-3 encoding into FSM implementation.
  • Synplify Pro and Identify tools upgraded to V-2023.09M-3.
  • Modelsim ME Pro and Questasim ME simulator tools upgraded to v2024.2.
  • Added support for the following Operating Systems:
    • RHEL/Alma 8.3-8.10
    • SUSE 12 SP5
    • Ubuntu 20.04.6
  • FlexLM license upgrade to v11.19.

PolarFire, RT PolarFire and PolarFire SoC Enhancements

  • PF_IOD_TX_CCC, PF_IOD_GENERIC_RX: Added Phase Direction parameter for BCLK/SCLK alignment

  • PF_DDR3, PF_DDR4: Added "CK/CA additive offset" parameter to the Training IP of the DDR controller
  • Project setting Default I/O technology LVCMOS 3.3V: Adds support for TRIBUFF_DIFF, BIBUF_DIFF by selecting an appropriate I/O standard
  • SPI-Flash programming support for IS25WP256D-JLLE

SmartHLS

  • SmartHLS now uses the Libero SoC Design Suite license. Need a separate license only for SmartHLS v2024.1 and earlier versions.
  • Improved SmartHLS Driver API to support multiple instances of the same SmartHLS-generated RTL module.
  • New Automatic On-Chip Instrumentation feature inserts Identify probes in SmartHLS-generated RTL module ports, and internal FIFOs to monitor occupancy levels. No need to specify each port individually.
  • ECC/RTG4 support for SmartHLS FIFOs, Data buffers, Line buffers, AXI4 target interface and error injection in simulation.
  • New pragma to ignore false loop dependencies and improve pipelining.

More Information

Libero SoC Design Suite Help Documentation

  • Click here to view the new Libero SoC Design Suite Help documentation, which provides robust search and navigation as well as HTML-based content.
  • Click here to download the latest Libero SoC Design Suite Help documentation (in HTML file format) for offline reference. Extract the contents of the .zip archive and open the index.html file in a web browser of your choice.

FPGA Design Resources

Click the following links to explore our other FPGA design resources:

Licensing

Libero software and DirectC license orders are now supported through Microchip purchasing portal. Most of the software tools and FPGA IP cores are freely available but some high-value IP cores and resources needed to work with high-density FPGAs require paid licenses. For more information, see Licensing.