21.2.1 HDL to Programming Flow

In libero.tcl, use the following commands to execute these tasks.

source ./parameters.tcl;

set libero_cmd "new_project \
                -location {./exprj} -name {exprj} \
                -family {$prj_family} -die {$prj_die} -package {$prj_package} \
                -speed {$prj_speed} \
                -hdl {VERILOG}";

eval file delete -force ./exprj;

eval $libero_cmd;

source ./design.tcl;

build_design_hierarchy;

set_root $prj_root;

For more information about HDL commands, see the HDL Tcl Commands.

In this step, timing constraints are derived. In libero.tcl, use the following command to derive timing constraints.

derive_constraints_sdc

For more information about applying constraints, see the Derive Constraints Tcl Commands.

In this step, the functionality of the HDL is verified before Synthesis using a test bench. In libero.tcl, use the following command to run pre-synthesis simulation.

run_tool -name {SIM_PRESYNTH}

As a best practice, use this command with the catch statement as shown in the following snippet.

if {[catch {run_tool -name {SIM_PRESYNTH}  }] } {
	  puts "SIM_PRESYNTH FAILED \n"
   } else {
	  puts "SIM_PRESYNTH PASSED \n"
   }  

For more information about adding pre-synthesis simulation parameters, see the run_tool command.

In this step, HDL is synthesized according to constraint files. In libero.tcl, use the following command to run Synthesis.

run_tool -name {SYNTHESIZE}

Use this command with the catch statement as shown in the following snippet.

if {[catch {run_tool -name {SYNTHESIZE}  }] } {
	  puts "SYNTHESIZE FAILED \n"
   } else {
	  puts "SYNTHESIZE PASSED \n"
   }  

For more information about adding Synthesis parameters, see the run_tool command.

In this step, the functionality of the HDL is verified after Synthesis using a test bench. In libero.tcl, use the following command to run post-synthesis simulation.

run_tool -name {SIM_POSTSYNTH}

Use this command with the catch statement as shown in the following snippet.

if {[catch {run_tool -name {SYNTHESIZE}  }] } {
	  puts "SIM_POSTSYNTH FAILED \n"
   } else {
	  puts "SIM_POSTSYNTH PASSED \n"
   }  

For more information about adding Synthesis parameters, see the run_tool command.

In this step, HDL is placed and routed according to constraint files. In libero.tcl, use the following command to run Place and Route.

run_tool -name {PLACEROUTE}

Use this command with the catch statement as shown in the following snippet.

if {[catch {run_tool -name {PLACEROUTE}  }] } {
	  puts "PLACEROUTE FAILED \n"
   } else {
	  puts "PLACEROUTE PASSED \n"
   }   

For more information about adding Place and Route parameters, see the run_tool command.

In this step, HDL is verified for timing closure. In libero.tcl, use the following command to run Timing Verification.

run_tool -name {VERIFYTIMING}

Use this command with the catch statement as shown in the following snippet.

if {[catch {run_tool -name {VERIFYTIMING}  }] } {
	  puts "VERIFYTIMING FAILED \n"
   } else {
	  puts "VERIFYTIMING PASSED \n"
   }    

For more information about adding Verify Timing parameters, see the run_tool command.

In this step, power verification is executed before generating the programming bit stream. In libero.tcl, use the following command for verifying the power consumption.

run_tool -name {VERIFYPOWER}

Use this command with the catch statement as shown in the following snippet.

if {[catch {run_tool -name {VERIFYPOWER}  }] } {
	  puts "VERIFYPOWER FAILED \n"
   } else {
	  puts "VERIFYPOWER PASSED \n"
   }  

For more information about adding Verify Power parameters, see the run_tool command.

In libero.tcl, use the following commands to execute these tasks.

run_tool -name {GENERATEPROGRAMMINGDATA}
generate_design_initialization_data  
run_tool -name {GENERATEPROGRAMMINGFILE}

export_bitstream_file \
         -file_name {test} \
         -format {STP DAT PPD } \
         -limit_SVF_file_size 0 \
         -limit_SVF_file_by_max_filesize_or_vectors {SIZE} \
         -svf_max_filesize {1024} \
         -svf_max_vectors {1000} \
         -trusted_facility_file 1 \
         -trusted_facility_file_components {FABRIC SNVM} \
         -zeroization_likenew_action 0 \
         -zeroization_unrecoverable_action 0

export_prog_job \
         -job_file_name {test} \
         -bitstream_file_type {TRUSTED_FACILITY} \
         -bitstream_file_components {FABRIC SNVM} \
         -zeroization_likenew_action 0 \
         -zeroization_unrecoverable_action 0 \
         -program_design 1 \
         -program_spi_flash 0 \
         -design_bitstream_format {PPD}

close_project -save 1

Use these commands with the catch statement as shown in the following snippet.

if {[catch {run_tool -name {GENERATEPROGRAMMINGDATA}  }] } {
	  puts "GENERATEPROGRAMMINGDATA FAILED \n"
   } else {
	  puts "GENERATEPROGRAMMINGDATA PASSED \n"
   }

if {[catch {generate_design_initialization_data}  }] } {
	  puts "DESIGN INITIALIZATION FAILED \n"
   } else {
	  puts "DESIGN INITIALIZATION PASSED \n"
   }        

if {[catch {run_tool -name {GENERATEPROGRAMMINGFILE}  }] } {
	  puts "GENERATEPROGRAMMINGFILE FAILED \n"
   } else {
	  puts "GENERATEPROGRAMMINGFILE PASSED \n"
   }

For more information about adding programming parameters, see the following.

• export_bitstream_file
• export_prog_job
• run_tool
• generate_design_initialization_data
• close_project