15.3 Introduction

Design debug is a critical phase of the FPGA design flow. Microchip’s SmartDebug tool complements design simulation by enabling verification and troubleshooting at the hardware level.

Using SmartDebug, you can debug Microchip FPGA arrays and SerDes without requiring an internal logic analyzer. SmartDebug can also capture FPGA device status, MSS register access, and flash and DDR memory content.

SmartDebug uses dedicated and specialized probe points built into the FPGA fabric to accelerate and simplify the debug process significantly. It also allows you to select or change different probe point on-the-fly without additional overhead, saving significant recompile time.

SmartDebug can be accessed within the Libero® design flow or as a standalone software application.

Important: This document is updated frequently. The latest version of this document is available at this location: Libero SoC Design Suite Documentation.

15.3.1 Supported Device Families

The following table lists the family of devices that SmartDebug supports. This guide covers all these device families. However, some information in this guide might apply to certain device families only. In this case, such information is clearly identified.
Table 15-24. Device Families Supported by SmartDebug
Device FamilyDescription
PolarFire®PolarFire FPGAs deliver the industry’s lowest power at mid-range densities with exceptional security and reliability.
RT PolarFireRT PolarFire is Microchip’s family of next-generation radiation-tolerant FPGAs that enable higher computing and connectivity throughput at 40 to 50% lower power than competing SRAM FPGAs.
PolarFire SoCPolarFire SoC is the first SoC FPGA with a deterministic, coherent RISC-V CPU cluster, and a deterministic L2 memory subsystem enabling Linux® and real-time applications.
SmartFusion® 2SmartFusion 2 addresses fundamental requirements for advanced security, high reliability, and low power in critical industrial, military, aviation, communications, and medical applications.
IGLOO® 2IGLOO 2 is a low-power mixed-signal programmable solution.
RTG4™RTG4 is Microchip's family of radiation-tolerant FPGAs.
Note: For SCB read operations with PolarFire devices, if the APB DRI bus performs an SCB read operation while SmartDebug is trying to read from the SCB, the data may get corrupted. If the PolarFire controller initiates a polled read, it polls for SCB read done register. After it acknowledges the done operation, it takes several CPU cycles to transfer the data. If the APB DRI interface initiates an SCB read operation during the transfer, the stored data becomes corrupt and SmartDebug may read corrupt data.

15.3.2 Supported Tools

The following table lists the device family support for SmartDebug tools. A check mark indicates that the tool is supported.

Table 15-25. Device Family Support for SmartDebug Tools
SmartDebug Support per Device FamilyPolarFire® and RT PolarFirePolarFire SoCSmartFusion® 2IGLOO® 2RTG4™ FPGAs
Active Probes✔️✔️✔✔✔
Debug DDR✔️✔️☓☓☓
Debug IOD✔✔☓☓☓
Debug SerDes☓☓✔✔✔
Debug SNVM✔✔☓☓☓
Debug Transceiver✔✔☓☓☓
Debug uPROM✔✔☓☓☓
Event Counter (needs FHB Auto Instantiation)✔✔✔✔✔
FPGA Hardware Breakpoint (needs FHB Auto Instantiation)✔✔✔✔✔
Frequency Monitor (needs FHB Auto Instantiation)✔✔✔✔☓
Live Probes✔✔✔✔️✔
Memory Debug✔✔✔✔✔
MSS Register Access☓✔☓☓☓
Probe Insertion (available only through Libero® flow)✔✔✔✔✔
TVS Monitor✔✔☓☓☓
View Flash Memory Content—eNVM Debug☓✔✔✔☓
Important: Observe the following:
  • Debug DDR is not supported for the MSS DDR subsystem. A separate tool is launched to support the debug features of the MSS DDR subsystem.
  • The contents of eNVM cannot be debugged in boot mode 0. Therefore, before using SmartDebug, Debug eNVM requires a device to be in an active boot mode (that is, a boot mode other than 0) and have a valid embedded software application running that enables the MPU.