10.1 Introduction

In the FPGA design world, constraint files are as important as design source files. Physical Design Constraints (PDC) are used to constrain I/O attributes, placement, and routing during the physical layout phase.

You can enter PDC commands manually using the Libero® SoC Text Editor. PDC commands can also be generated by the Libero SoC interactive tools. The I/O Attribute Editor is the interactive tool for making the I/O attributes changes, and the Chip Planner is the interactive tool for making the floor-planning changes. When changes are made in the I/O Attribute Editor or the Chip Planner, the PDC file(s) are updated to reflect these changes. These PDC commands are used as part of a script file to constrain the Place-and-Route step of your design.