15.3.4 Frequently Asked Questions

If the Embedded Flash Memory failed verification when executing the PROGRAM_NVM, VERIFY_NVM or PROGRAM_NVM_ACTIVE_ARRAY action, the failing page may be corrupted. To confirm and address this issue:

1. In the Inspect Device window click View Flash Memory Content.
2. Select the Flash Memory block and client (or page range) to retrieve from the device:
   1. Click Read from Device; the retrieved data appears in the lower part of the window.
   2. Click View Detailed Status.
      Note: You can use the check_flash_memory and read_flash_memory Tcl commands to perform diagnostics similar to the preceding commands.
   3. To reset the corrupted NVM pages, either re-program the pages with your original data or ‘zero-out’ the pages by using the Tcl command recover_flash_memory.

If the Embedded Flash Memory failed verification when executing a VERIFY_NVM or VERIFY_NVM_ACTIVE_ARRAY action, the failure may be due to the change of content in your design. To confirm this, repeat te preceding steps.

If the Analog System is not working correctly, it may be due the following:

• System supply issue. To troubleshoot:
  1. Physically verify that all the supplies are properly connected to the device and they are at the proper level. Then confirm by running the Device Status.
  2. Physically verify that the relevant channels are correctly connected to the device.
• Analog system is not properly configured. You can confirm this by examining the Analog System.

If the ADC is sampling all zero values then the wrong analog pin may be connected to the system, or the analog pin is disconnected. If that is not the case and the ADC is not sampling the correct value, it may be due to the following:

• System supply issues: Run the device status to confirm.
• Analog system is not configured at all: To confirm, read out the ACM configuration and verify if the ACM content is all zero.
• Analog system is not configured correctly: To confirm:
  1. Read out the ACM configuration and verify that the configuration is as expected.
  2. Once analog block configuration has been confirmed, you can use the sample_analog_channel Tcl command for debug sampling of the analog channel with user-supplied sampling parameters.
  3. If you have access to your Analog System Builder settings project (<Libero IDE project>/Smartgen/AnalogBlock), you may use the compare function provided by the tool.

You must provide the PDB file with a User Pass Key to unlock the device and continue debugging.

If you do not have a PDB with User Pass Key but you know the Pass Key value, you can create a PDB file in FlashPro.

You can export three reports from the SmartDebug GUI: Device Status, Client Detailed Status from the NVM, or the Compare Client Content report from the NVM. Each of those reports can be saved and printed.

For more information about Tcl commands supported by SmartDebug, see the Tcl Commands Reference Guide .

To monitor a static or pseudo-static signal:

1. Add the signal to the Active Probes tab.
2. Select the signal in the Active Probes tab, right click, and choose Poll....

   

3. In the Pseudo-static Signal Polling dialog box, choose a value in Polling Setup and click Start Polling.

   

To force a signal to a new value:

1. In the SmartDebug window, click Debug FPGA Array.
2. Click the Active Probes tab.
3. Select the signal from the selection panel and add it to Active Probes tab.

   

4. Click Read Active Probe to read the value.
5. In the Write Value column, enter the value to write to the signal and then click Write Active Probes.

   

If FHB IP is auto-instantiated in the design, you can use the Event Counter in the Live Probes tab to count the transitions on a signal.

To count the transitions on a signal:

1. Assign the desired signal to Live Probe Channel A.
2. Click the Event Counter tab and check the Activate Event Counter check box.

   

You can monitor a clock signal from the Live Probe tab when the design is synthesized and compiled with FHB Auto Instantiation turned on in Project Settings dialog box.

In the Live Probe tab, SmartDebug allows you to:

1. Measure all the FABCCC GL clocks by clicking the User Clock Frequencies tab, as shown in the following figure.

   

2. Monitor frequencies of any probe points by:
   1. Assigning the desired signal to Live Probe Channel A.
   2. Selecting the Frequency Monitor tab as shown in the following figure and checking the Activate Frequency Meter check box.

   

You can perform PRBS and loopback tests using the Debug SerDes option in SmartDebug.

To perform a PRBS test, in the Debug SerDes dialog box, select PRBS Test to run a PRBS test on-die or off- die For more information, see Debug SerDes – PRBS Test.

To perform a PRBS test, in the Debug SerDes dialog box, select PRBS Test to run a PRBS test on-die or off- die. For more information, see Debug SerDes – PRBS Test.

To perform a loopback test, in the Debug SerDes dialog box, select Loopback Test to run a near end serial loopback /far end PMA Rx to Tx loopback test. For more information, see Debug SerDes – Loopback Test.

To read RAM content:

1. In the Debug FPGA Array dialog box, click the Memory Blocks tab.
2. Select the memory block to be read from the selection panel on the left of the window.

   

   An L in the icon next to the block name indicates that it is a logical block, and a P in the icon indicates that it is a physical block. A logical block displays three fields in the Memory Blocks tab: User Design Memory Blocks, Data Width, and Port Used. A physical block displays two fields in the Memory Blocks tab: User Design Memory Block and Data Width.

3. Add the block in one of the following ways:
   • Click Select.
   • Right click and choose Add.
   • Drag the block to the Memory Blocks tab.
4. Click Read Block to read the content of the block.

   

To change the content of LSRAM or USRAM:

1. In the SmartDebug window, click Debug FPGA Array.
2. Click the Memory Blocks tab.
3. Select the memory block from the selection panel on the left of the window.

   

   An L in the icon next to the block name indicates that it is a logical block, and a P in the icon indicates that it is a physical block. A logical block displays three fields in the Memory Blocks tab: User Design Memory Blocks, Data Width, and Port Used. A physical block displays two fields in the Memory Blocks tab: User Design Memory Block and Data Width.

4. Add the memory block in one of the following ways:
   • Click Select.
   • Right click and choose Add.
   • Drag the block to the Memory Blocks tab.
5. Click Read Block. The memory content matrix is displayed.
6. Select the memory cell value that you want to change and update the value.
7. Click Write Block to write to the device.

   

You can read the SerDes health check using the following Debug SerDes options:

1. Review the Configuration Report, which returns PMA Ready, TxPLL status, and RxPLL status. For SerDes to function correctly, PMA ready should be true, and TxPLL and RxPLL status should be locked. The Configuration Report can be found in the Debug SerDes dialog box under Configuration. See Debug SerDes (SmartFusion 2, IGLOO 2, and RTG4).

   

2. Run the PRBS Test, which is a Near End Serial Loopback tests on selected lanes. This should result in 0 errors in the Cumulative Error Count column. See Debug SerDes – PRBS Test.

UFC is the User FlashROM Configuration file, generated by the FlashROM configurator; it contains the partition information set by the user. It also contains the user-selected data for region types with static data.

However, for AUTO_INC and READ_FROM_FILE, regions the UFC file contains only:

• Start value, end value, and step size for AUTO_INC regions
• File directory for READ_FROM_FILE regions

EFC is the Embedded Flash Configuration file, generated by the Flash Memory Builder in the Project Manager Catalog; it contains the partition information and data set by the user.

Both UFC and EFC information is embedded in the PDB when you generate the PDB file.

When your FPGA fabric is programmed, you will see the following statement under Device State in the Device Status report:

FPGA Array Status: Programmed and Enabled

If the FPGA fabric is not programmed, the Device State shows:

FPGA Array Status: Not Enabled

To know if your NVM is programmed, read out and view the NVM content or perform verification with the PDB file.

To examine the NVM content, see the FlashROM Memory Content dialog box.

You must load your PDB into your FlashPro project to view the Embedded Flash Memory content in the Client partition. To view NVM content in the client partition:

1. Load your PDB into your FlashPro project.
2. Click Inspect Device.
3. Click View Flash Memory Content.
4. Choose a block from the drop-down menu.
5. Select a client.
6. Click Read from Device. The Embedded Flash Memory content from the device appears in the Flash Memory dialog box.

When Embedded Flash Memory is corrupted, checking Embedded Flash Memory may return with any or all of the following page status:

• ECC1/ECC2 failure
• Page write count exceeds the 10-year retention threshold
• Page write count is invalid
• Page protection is set illegally (set when it should not be)

See the How do I interpret data in the Flash Memory (NVM) Status Report? topic for details.

If your Embedded Flash Memory is corrupted, you can recover by reprogramming with original design data. Alternatively, you can ‘zero-out’ the pages by using the Tcl command recover_flash_memory.

Embedded Flash Memory corruption occurs when Embedded Flash Memory programming is interrupted due to:

• Supply brownout; monitor power supplies for brownout conditions. For SmartFusion, monitor the VCC_ENVM/VCC_ROSC voltage levels; for Fusion, monitor VCC_NVM/VCC_OSC.
• Reset signal is not properly tied off in your design. Check the Embedded Memory reset signal.

Reprogram with original design data or ‘zero-out’ the pages by using the Tcl command recover_flash_memory.

JTAG IR-Capture value contains private and public device status values. The public status value in the value read is ISC_DONE, which indicates if the FPGA Array is programmed and enabled.

The ISC_DONE signal is implemented as part of IEEE 1532 specification.

ECC is the Error Correction Code embedded in each Flash Memory page. ECC1 – One bit error and correctable.

ECC2 – Two or more errors found, and not correctable.

When invalid firmware is loaded into eNVM in SmartFusion 2 devices, Arm® Cortex®-M3 will not be able to boot and issues reset to MSS continuously. eNVM content using View Flash Memory content will read zeroes in SmartDebug.

To verify that your FlashROM is programmed, read out and view the FlashROM content or perform verification with the PDB file by selecting the VERIFY or VERIFY_FROM action in FlashPro.

To compare the serialization data, you can read out the FlashROM content and visually check data in the serialization region. Note that a serialization region can be an AUTO_INC or READ_FROM_FILE region.

For serialization data in the AUTO_INC region, check to make sure that the data is within the specified range for that region.

For READ_FROM_FILE region, you can search for a match in the source data file.

To determine the programmed security settings, run the Device Status option from the Inspect Device dialog and examine the Security Section in the report.

This section lists the security status of the FlashROM, FPGA Array, and Flash Memory blocks.

The Device Status Report generated from the FlashPro SmartDebug Feature contains the following sections:

• IDCode
• User Information
• Device State
• Factory Data
• Security Settings

The Embedded Flash Memory (NVM) Status Report generated from the FlashPro SmartDebug feature consists of the page status of each NVM page. For example:

Flash Memory Content [ Page 34 to 34 ] 
FlashMemory Page #34:
Status Register(HEX): 00090000
Status ECC2 check: Pass