13 Introduction

SmartTime is a Libero® SoC interactive gate-level static timing analysis tool that allows you to visualize and identify timing issues in your designs. Using this tool, you can evaluate how close you are to meeting your timing requirements, create custom sets to track, set timing exceptions to obtain timing closure, and define cross-probe paths with other tools. Key SmartTime features allow you to:

  • Perform complete timing analysis of your design to ensure that your designs meet all timing constraints and operate at the desired speed, with the appropriate amount of margin across all operating conditions.
  • Browse through your design’s various clock domains to examine the timing paths and identify those that violate your timing requirements.
  • Create customizable timing reports.
  • Navigate directly to the paths responsible for violating your timing requirements.
Note: Creating and editing timing constraints are handled in a separate Timing Constraints Editor. For more information, see the Timing Constraints Editor User Guide .

Supported Device Families

The following table lists the family of devices that Libero SoC supports. This guide covers all these device families. However, some information in this guide might apply to certain device families only. In this case, such information is clearly identified.
Table 13-1. Device Families Supported by Libero® SoC
Device FamilyDescription
PolarFire®PolarFire FPGAs deliver the industry’s lowest power at mid-range densities with exceptional security and reliability.
PolarFire SoCPolarFire SoC is the first SoC FPGA with a deterministic, coherent RISC-V® CPU cluster, and a deterministic L2 memory subsystem enabling Linux® and real-time applications.
SmartFusion® 2SmartFusion 2 addresses fundamental requirements for advanced security, high reliability, and low power in critical industrial, military, aviation, communications, and medical applications.
IGLOO® 2IGLOO 2 is a low-power mixed-signal programmable solution.
RTG4™RTG4 is Microchip's family of radiation-tolerant FPGAs.
Important: This document is updated frequently. The latest version of this document is available at this location: Libero SoC Design Suite Documentation.