11 Introduction

Chip Planner is a graphical interface tool that provides a Chip View and a Netlist View of your designs.

The Chip View allows you to create regions, edit regions, and make logic assignments to regions. It is a floorplanning tool used to improve the timing performance and routability of your design by providing maximum control over your design object placement.

The Netlist View provides a schematic view of the design that allows you to examine the routing of the nets and reveal any routing congestions.

You can also cross-probe from SmartTime into Chip Planner to browse your design and look into timing problems.

Use Chip Planner to:

• View macro assignments made during layout.
• Assign, unassign, or move macros.
• Lock macro assignments.
• View net connections using a ratsnest view.
• View architectural boundaries.
• View and edit silicon features, such as I/O banks.
• Create Regions and assign macros or nets to regions (floorplanning).
• View logic placement and net connections to investigate timing problems together with SmartTime’s Cross-Probing feature.
• View the hierarchical netlist after Synthesis and the flattened netlist after Compile.
• Create logical cones for debugging and detailed analysis.

Run Synthesis and Compile Netlist on your design before invoking Chip Planner. You can invoke Chip Planner for floorplanning after running Place and Route to improve routability and remove congestion.

When floorplanning, analyze your design to see whether certain logic can be grouped within regions. Placement of regions are especially useful for hierarchical designs, with sufficient local connectivity within a block. If your timing analysis indicates several paths with negative slack, you can group the logic included in these paths into their own regions. This forces the placement of logic close together within the path and may improve timing performance of the design.