1.3 What's New in SmartHLS 2024.2

Release Date: September, 2024

Announcements

A webinar on “Migrating Third-Party HLS Designs to Microchip FPGAs Using SmartHLS Compiler” is now available on-demand at the following location: https://event.on24.com/wcc/r/4520819/679F87D10C54DF2B9A2294739D5CE006

Software Features and Enhancements

The following new features are available in the SmartHLS 2024.2 release.
General Updates
  • SmartHLS now supports the same operating systems as Libero 2024.2.
  • Starting version 2024.2, SmartHLS no longer requires a separate license. SmartHLS is now supported using the Libero SoC Design Suite license. For SmartHLS 2024.1 and earlier, you need to upgrade your Libero license. Your upgraded Libero license is available for download after the release of Libero SoC 2024.2. With the upgraded Libero license, you can use SmartHLS 2024.1 and earlier without a separate SmartHLS license.

    To download your upgraded Libero license, log on to your Microchip Direct account. For instructions on how to setup a Libero license, see the Libero SoC Software Download and License Installation Guide Ordering and Downloading a License.

  • Core compiler has been upgraded from LLVM 3.5.2 to 14.0.6.
  • SmartHLS compiler has been enhanced to enable compile-time generation of Look-up Table (LUT) values by parsing user C++ code that generates the table values, before generating the RTL module. Using pre-compiled constant look-up tables is a typical design practice to save resources, and this ease-of-use enhancement avoids manually hard-coding the table or copying and pasting from an external script or program used to generate the values. Some functions (e.g. Gamma Correction and Bilateral Filter) in the SmartHLS Vision Library in GitHub use this technique.
  • The SmartHLS output directory can now be specified using a command-line argument. (Earlier, this was always set to hls_output). This can be useful when experimenting with different pragmas or settings. Different output directories can be used to compare results.
    $> shls hw --output_dir my_hls_output_1
    $> shls hw -o my_hls_output_2
Improved Driver API Support
SmartHLS Driver API now supports for multiple instances of the same SmartHLS-generated HDL+ component. For example, this allows the same HDL+ component to be copied and pasted within a SmartDesign canvas. The API directly uses the base address to select the module.
foo_hls_driver(..., FOO0_BASE_ADDR);
foo_hls_driver(..., FOO1_BASE_ADDR);
For more information, see API Driver Functions for AXI4 Target.
Automatic On-Chip Instrumentation
The Automatic On-Chip Instrumentation feature has been introduced.
By simply adding the following flag in the Makefile, SmartHLS automatically adds Identify probes to the SmartHLS-generated Verilog. Users will not have to specify each port individually.
HLS_INSTRUMENT_ENABLE=1
The following features are currently available:
  • Users can expose signals coming in and out of the SmartHLS modules, as well as all the activity of all the internal FIFOs.
  • Debugging log levels (-v, -vv, -vvv) can be specified to control the amount of instrumentation. Similar to software but applied to hardware design.
  • Real-time monitoring of FIFO occupancy is possible. This helps in providing immediate insights into system performance.
    Figure 1-1. Real-time FIFO Occupancy
Improvements to SmartHLS IDE
  • Users can now launch a Windows Powershell terminal from within the SmartHLS IDE with all environment setup to enable users to script the SmartHLS usage and run from the command-line.
  • SmartHLS Software Profiling feature is removed.
ECC/RTG4 support
  • Error Code Correction (ECC) protected memory is now supported for SmartHLS FIFOs, data buffers, and line buffers.
  • ECC support is added for AXI4 Target Interface.
  • New ECC error simulation feature for RTG4 LSRAM is now available as an alpha feature. For more information, see Error Simulation.
SmartHLS Open Source Libraries
hls::dsp:
New library has been added with the FFT function and on-board examples on the Icicle Kit, Discovery Kit, and BeagleV-Fire.
hls::vision
The following new functions and examples have been added to the Vision library.
  • Gamma Correction
  • 2D Convolution
  • Histogram
  • ImageEnhance (Color and brightness adjustments)
  • BilateralFilter
hls::math
Added sin_performance example, where the same source code runs on multiple boards such as the following:
  • BeagleV-Fire (upstream changes to beagleboard.org approved, waiting for them to merge)
  • Discovery Kit
  • Icicle Kit
New Support for Assertions
Developers can now call assert( ) in C++ to generate RTL assertions in the generated Verilog for simulation purposes, further improving the debugging process. For more information, see Standard C Library Assertions (assert.h).
C++     : assert(a < b);
Verilog : $fatal(1, "[%s:%d] (a < b) failed to be met!\n",`__FILE__, `__LINE__ );
New Pragma
  • A new Loop Dependence pragma has been introduced to allow users override loop-carried dependency analysis result of the tool.
    #pragma HLS loop dependence argument(a) type(inter) direction(RAW) dependent(false)
    for (int i = 0; i<N; i++) {
       b[i] = a[i];
       a[i+offset] = 0;
    }
  • Allows the use of compile-time defined integers and meta functions as pragma parameter values. For example, at Line 8, the meta function decides at compile-time what unroll factor to use based on the value of template parameter N and a maximum value of 10. In this case the function is a simple bound (max) operation that could be used to limit the amount of loop unrolling to 10. This adds more programmability to pragma integer arguments.
    template <unsigned int N, unsigned int MAX> struct Bounds {
        static constexpr unsigned int value = N > MAX ? MAX : N;
    };
     
    template <unsigned int N>
    int foo(...) {
       ...
       #pragma HLS loop unroll factor(Bounds <N, 10>::value)
       for (int i = 0; i < N; ++i) {
          ...
       }
       ...
    }

Resolved Issues

The following issues have been resolved in the 2024.2 version:
  • Fixed a fatal error that occurred when running a low clock period constraint.
  • Fixed various issues related to the Dataflow feature.
  • Fixed an issue that occurred when using the values generated from one pipelined loop in another.
  • Added a warning message when an array is too big to be partitioned.
  • Fixed the incorrect reporting of size and depth in the I/O Memories report.
  • Improved the SmartHLS Function and Loop Scheduling Results report. The missing definitions for Trip count, Iteration Latency and Total Latency are now added in the documentation.
  • Fixed broken online and offline documentation links in SmartHLS IDE. Both online and offline links are now directed to version 2024.2.
  • Fixed external library compiling issue on Eclipse IDE by adding the PATH to SmartHLS.bat
  • Resolved the confusion on how to launch the SmartHLS IDE by moving the incorrect file to a different location. Users must now run SmartHLS.bat instead of SmartHLS.exe.
  • Removed outdated .job files from Training 4 Vector Add SoC.