3.5.1.5 SmartHLS Constraints

SmartHLS™ also supports user constraints to guide hardware generation. Whereas pragmas are applied directly on the source code for optimizations that are specific and local to the software construct that it is being applied on (function, loop, memory, argument, and so on), constraints are used for settings that will be globally applied to the entire program (for example setting the target FPGA, target clock period).

Each project specifies its constraints in the config.tcl file in the project directory. This file is automatically generated by theSmartHLS IDE. To modify the constraints, click the HLS Constraints button:

The following window will open:

You can add, edit, or remove constraints from this window. Select a constraint type from the first drop-down menu. If you want more information about a constraint, click the Help button, which will open the corresponding Constraints Manual page.

An important constraint is the target clock period (shown as Set target clock period in the drop-down menu). With this constraint, SmartHLS schedules the operations of a program to meet the specified clock period. When this constraint is not given, SmartHLS uses the default clock period for each device, as shown below.

Details of all SmartHLS constraints are given in the Constraints Manual.