5.13 References

The Archive Project dialog box enables you to create an archive (*.zip file) of your existing project and save it at the specified location. This is useful if you want to create a quick zip file of your project. Archive Project and Save As Project are functionally equivalent; however, if you are saving your Libero application to the SVN repository, it is important to archive your project. When you do an SVN checkout after checkin, timestamps might be outdated, and the tool states will remain invalidated. Archive Project helps in retaining the tool states by preserving the database in compressed format.

To access this dialog box, choose Archive Project from the Project menu.

Project Location. Accept the default location or browse to a new location where you want to save the archive (*.zip) file. The *.zip file is named <project_name>.zip.

Copy links locally. Check this check box to copy the links from your current project into your archive. Otherwise, the links will not be copied and you must add them manually.

Files. Specifies the kind of files that are archived.

• All. Includes in the archive all your project and source files; the state of the project is retained.
• Project files only: Includes in the archive only the project-related information required to retain the state of the project.
• Source files only: Includes in the archive only the source files. This means the configuration of all the tools in the toolchain is retained but the states are not. Source files means constraint information and component information available in the component, hdl and smartgen directories.

Files are archived for different selections as shown in the following table.

SmartDesign supports automatic creation of data driven configurators based on HDL generics/parameters. You can add a bus interface from your HDL module, or you can add it from the Catalog.

To add a bus interface using your custom HDL block:

If your block has all the necessary signals to interface with the AMBA bus protocol (such as address, data, and control signals):

1. Right-click your custom HDL block and choose Create Core from HDL. The Libero SoC creates your core and asks if you want to add bus interfaces.
2. Click Yes to open the Edit Core Definition dialog box and add bus interfaces. Add the bus interfaces, as necessary.
3. Click OK to continue.

Now your instance has a proper AMBA bus interface on it. You can manually connect it to the bus or let Auto Connect find a compatible connection.

To add (or modify) a bus interface to your Component:

1. Right-click your Component and choose Edit Core Definition. The Edit Core Definition dialog box opens, as shown in the following figure.

   

2. Click Add Bus Interface. Select the bus interface you want to add and click OK.
3. If necessary, edit the bus interface details.
4. Click Map by Name to map the signals automatically. Map By Name attempts to map any similar signal names between the bus definition and pin names on the instance. During mapping, bus definition signal names are prefixed with text entered in the Map by Name Prefix field.
5. Click OK to continue.

Configuration Parameters

Signal Map Definition

The signal map of the bus interface specifies the pins on the instance that correspond to the bus definition signals. The bus definition signals are shown on the left, under the Bus Interface Definition. This information includes the name, direction and required properties of the signal.

The pins for your instance are shown in the columns under the Component Instance. The signal element is a drop-down list of the pins that can be mapped for that definition signal.

If the Req field of the signal definition is Yes, you must map it to a pin on your instance for this bus interface to be considered legal. If it is No, you can leave it unmapped.

In the Libero SoC, from the View menu choose Windows > Catalog.

The Catalog displays a list of available cores, buses, and macros.

From the Catalog, you can create a component from the list of available cores, add a processor or peripheral, add a bus interface to your SmartDesign component, instantiate simulation cores or add a macro (Arithmetic, Basic Block, and so on.) to your SmartDesign component.

1. Double-click a core to configure it and add it to your design. Configured cores are added to your list of Components/Modules in the Design Explorer.
2. Check the Simulation Mode check box to instantiate simulation cores in your SmartDesign Testbench. Simulation cores are basic cores that are useful for stimulus, such as driving clocks, resets, and pulses.

Viewing Cores in the Catalog

The font indicates the status of the core:

• Plaintext - In vault and available for use
• Asterisk after name (*) - Newer version of the core (VLN) available for download
• Italics - Core is available for download but not in your vault
• Strikethrough - core is not valid for this version of Libero SoC

The colored icons indicate the license status. Blank means that the core is not license protected in any way. Colored icons mean that the core is license protected, with the following descriptions.

Green Key - Fully licensed; supports the entire design flow.

Yellow Key - Has a limited or evaluation license only. Precompiled simulation libraries are provided, enabling the core to be instantiated and simulated within Libero SoC. Using the Evaluation version of the core it is possible to create and simulate the complete design in which the core is being included. The design is not synthesizable (RTL code is not provided). No license feature in the license.dat file is needed to run the core in evaluation mode. You can purchase a license to generate an obfuscated or RTL netlist.

Yellow Key with Red Circle - License is protected. You are not licensed to use this core.

Catalog Options

Click the UI control button

Import a core from a file when:

• You do not have access to the internet and cannot download the core, or
• A core is not completed and not posted to the web (you have an evaluation core)

Manually Downloading MegaVaults and Individual CPZ files

When Libero is used in an environment without automatic access to Microchip's online IP repositories via the Internet; see this article explaining how to download MegaVaults and individual CPZ files.

Output propagation delay is affected by both the capacitive loading on the board and the I/O standard. The I/O Attribute Editor in Chip Planner provides a mechanism for setting the expected capacitance to improve the propagation delay model. SmartTime automatically uses the modified delay model for delay calculations.

To change the output port capacitance and view the effect of this change in SmartTime Timing Analyzer, refer to the following example. The following figure shows the delay from DFN1 to output port Q. It shows a delay of 6.603 ns based on the default loading of 5 pF.

If your board has output capacitance of 15 pf on Q, you must perform the following steps to update the timing number:

1. Open the I/O Attribute Editor and change the output load to 15 pf.

   

2. Select File > Save.
3. Select File > Close.
4. Open the SmartTime Timing Analyzer.

You can see that the Clock to Output delay changed to 5.952 ns.

The Core Manager only lists cores that are in your current project. If any of the cores in your current project are not in your vault, you can use the Core Manager to download them all at once.

For example, if you download a sample project and open it, you might not have all the cores in your local vault. In this instance you can use the Core Manager to view and download them with one click. Click Download All to add any missing cores to your vault. To add any individual core, click the green download button.

Configure Security Locks for Production is a GUI-based tool that guides the user on how to configure the Permanent Locks for Production. The wizard has six steps/pages executed in sequential order. One Time Programmable (OTP) settings in the Permanent Locks page are applied to configured Security settings from the Configure Security tool. The subsequent pages have read only fields, which will be affected by Permanent Lock settings. These settings can only be configured by the Configure Security tool.

If you configure any Permanent Lock settings, you will be forced to go through each page to review the Security settings to make sure they are as desired. The settings cannot be changed once they are programmed.

1. Permanent Locks and One-way Passcode
2. User keys in Configure Security
3. Update Policy in Configure Security
4. Debug Policy in Configure Security
5. Microsemi Factory Access in Configure Security
6. JTAG/SPI Slave Commands Policy in Configure Security

Summary Window

The summary window displays the summary of the current page configuration settings. Based on the selection made in the first page, the summary for the subsequent pages change. The window will scroll to the current page as you move from page to page.

Back

Click Back to return to the previous step.

Next

Click Next to proceed to the next step.

Finish

Click Finish to complete the configuration after executing the all the steps in sequential order.

Save Summary to File

Click Save Summary to File to save the display in the Summary field to a file.

Designer in Libero SoC cannot import files from outside your project without copying them to your local project folder. You might import source files from other locations, but they are always copied to your local folder. Designer in Libero SoC always audits the local file after you import; it does not audit the original file.

When the Project Manager asks you if you want to copy files "locally", it means 'copy the files to your local project folder'. If you do not wish to copy the files to your local project folder, you cannot import them. Your local project folder contains files related to your Libero SoC project.

Files copied to your local folders are copied directly into their relevant directories: netlists are copied to the synthesis folder; source files are copied to hdl folder, constraint files to constraint folder, and so on. The files are also added to the Libero SoC project and appear in the Files tab.

Use this dialog box to enter a clock constraint setting.

It displays a typical clock waveform with its associated clock information. You can enter or modify this information and save the final settings as long as the constraint information is consistent and defines the clock waveform completely. The tool displays errors and warnings if information is missing or incorrect.

To open the following Create Clock Constraint dialog box from the SmartTime Constraints Editor, choose Constraints > Clock.

Clock Source

Enables you to choose a pin from your design to use as the clock source.

The drop-down list is populated with all explicit clocks. You can also select the Browse button to access all potential clocks. The Browse button displays the Select Source Pins for Clock Constraint Dialog Box.

Clock Name

Specifies the name of the clock constraint. This field is required for virtual clocks when no clock source is provided.

Period

When you edit the period, the tool automatically updates the frequency value. The period must be a positive real number. Accuracy is up to 3 decimal places.

Frequency

When you edit the frequency, the tool automatically updates the period value.

The frequency must be a positive real number. Accuracy is up to 3 decimal places.

Starting Clock Edge Selector

Click the Up or Down arrow to use the rising or falling edge as the starting edge for the created clock.

Offset

Indicates the shift (in nanoseconds) of the first clock edge with respect to instant zero common to all clocks in the design.

The offset value must be a positive real number. Accuracy is up to 2 decimal places. Default value is 0.

Duty Cycle

This number specifies the percentage of the overall period that the clock pulse is HIGH.

The duty cycle must be a positive real number. Accuracy is up to 4 decimal places. Default value is 50%.

Add this clock to existing one with same source

Check this box if you want to add a new clock constraint on the same source without overwriting the existing clock constraint. The new clock constraint name must be different than the existing name. Otherwise, the new constraint will overwrite the existing one even if you check this box.

Comment

Enables you to save a single line of text that describes the clock constraints purpose.

See Also

Specifying Clock Constraints

Use this dialog box to find and choose the clock source from the list of available pins.

To open the Select Source Pins for the following Clock Constraint dialog box from the SmartTime Constraints Editor, click the Browse button to the right of the Clock source field in the Create Clock Constraint dialog box.

Available Pins

The list box displays the available pins. If you change the pattern value, the list box shows the available pins based on the filter.

Use Add, Add All to add the pins from the Available Pins list to Assigned Pins or Remove, Remove All to delete the pins from the Assigned Pins list.

Assigned Pins

Displays pins selected from the Available Pins list. Select Pins from this list and click OK to add the Source Pins for Clock Constraint.

See Also

Specifying clock constraints

Specifying clock constraints is the most effective way to constrain and verify the timing behavior of a sequential design. Use clock constraints to meet your performance goals.

To specify a clock constraint:

1. Add the constraint in the editable constraints grid or open the Create Clock Constraint dialog box using one of the following methods:
   • Click the
     
     icon in the Constraints Editor.
   • Right-click the Clock in the Constraint Browser and choose Add Clock Constraint.
   • Double-click Clock in the Constraint Browser.
   • Choose Clock from the Constraints drop-down menu (Constraints > Clock).

     The following Create Clock Constraint dialog box appears.

   

2. Select the pin to use as the clock source. You can click the Browse button to display the following Select Source Pins for Clock Constraint Dialog Box.
   Note: Do not select a source pin when you specify a virtual clock. Virtual clocks can be used to define a clock outside the FPGA that is used to synchronize I/Os.

   Use the Choose the Clock Source Pin dialog box to display a list of source pins from which you can choose. By default, it displays the explicit clock sources of the design. To choose other pins in the design as clock source pins, select Filter available objects - Pin Type as Explicit clocks, Potential clocks, All Ports, All Pins, All Nets, Pins on clock network, or Nets in clock network. To display a subset of the displayed clock source pins, you can create and apply a filter.

   Multiple source pins can be specified for the same clock when a single clock is entering the FPGA using multiple inputs with different delays.

3. Click OK to save these dialog box settings.
4. Specify the Period in nanoseconds (ns) or Frequency in megahertz (MHz).
5. Modify the Clock Name. The name of the first clock source is provided as default.
6. Modify the Duty cycle, if needed.
7. Modify the Offset of the clock, if needed.
8. Modify the first edge direction of the clock, if needed.
9. Select the check box for Add this clock to an existing one with the same source, if needed.
10. Click OK. The new constraint appears in the Constraints List.
    Note: When you choose File > Save, the Timing Constraints Editor saves the newly created constraint in the database.

Specifying a generated clock constraint enables you to define an internally generated clock for your design and verify its timing behavior. Use generated clock constraints and clock constraints to meet your performance goals.

To specify a generated clock constraint:

1. Open the Create Generated Clock Constraint dialog box using one of the following methods:
   1. Click the
      
      icon.
   2. Right-click the Generated Clock in the Constraint Browser and choose Add Generated Clock.
   3. Double-click the Generated Clock Constraints grid. The following Create Generated Clock Constraint dialog box appears.

      

2. Select a Clock Pin to use as the generated clock source. To display a list of available generated clock source pins, click the Browse button. The following Select Generated Clock Source dialog box appears.

   

3. Specify a Reference Pin. To display a list of available clock reference pins, click the Browse button. The Select Generated Clock Reference dialog box appears.
4. Specify the Generated Clock Name (optional).
5. Specify the values to calculate the generated frequency: a multiplication factor and/or a division factor (both positive integers).
6. Specify the orientation of the generated clock edges based on the reference edges by entering values for the edges and the edge shifts. This is optional.
7. Specify the first edge of the generated waveform either same as or inverted with respect to the reference waveform.
8. Specify the PLL output and PLL feedback pins if an External feedback is used to generate the clock.
9. Specify the Phase shift applied by the PLL in degrees.
10. Specify the Master Clock, if you want to add this to an existing one with the same source.
11. Click OK. The new constraint appears in the Constraints List.

    Tip: From the File menu, choose Save to save the newly created constraint in the database.

The Design Hierarchy tab displays a hierarchical representation of the design based on the source files in the project. It also displays elaborated hierarchy constructed by propagating correct values for parameters and generics. The software continuously analyzes the source files and updates the content. The following Design Hierarchy tab displays the structure of the modules and components as they relate to each other along with parameter/generic names and its values on the tooltip for which the module is instantiated. It also displays architecture name for a given entity and Configuration for VHDL modules.

A module can have multiple elaborations depending on the different parameters/generics used in the instantiation of the module and all these elaborated modules will be shown in the Design Hierarchy. The parameterized instantiated module will be shown as elab<num>:<modulename>.

Modules are instantiated with their actual names in the SmartDesign. If a module with elaborated name in the Design Hierarchy must be instantiated in the SmartDesign, an instance of the original module is created in the SmartDesign. The following figure shows the design hierarchy with elaborated modules.

Modules which are not part of the elaboration will be shown in the complete hierarchy but they remain grayed out. When you create a core from a module, all the elaborated modules of that module will be shown as HDL+ core modules. You can get the parameter value of an elaborated module by selecting Show Module parameters on the right-click menu of the elaborated module.

Note: Synthesis output will be the same for different elaborations of the same module, that is elab0:module1 and elab1:module1 will have the same synthesis output. When one of the elaborated modules is set as root, all the elaborations will be highlighted in the Design Hierarchy, as shown in the following figure.

You can change the display mode of the Design Hierarchy by selecting Components or Modules from the Show drop-down list. The components view displays the entire design hierarchy; the modules view displays only schematic and HDL modules.

You can build the Design Hierarchy and Simulation Hierarchy by clicking the Build Hierarchy button.

A yellow icon

To view the location of a component, right-click and choose Properties. The Properties dialog box displays the path name, created date, and last modified date.

All integrated source editors are linked with the SoC software. If a source is modified and the modification changes the hierarchy of the design, the Build Hierarchy automatically updates to reflect the change.

If you want to update the Design Hierarchy, from the View menu, choose Refresh Design Hierarchy.

To open a component:

Double-click a component in the Design Hierarchy to open it. Depending on the block type and design state, several possible options are available from the right-click menu. You can instantiate a component from the Design Hierarchy to the SmartDesign Canvas. See the SmartDesign User Guide for more information.

Icons in the Hierarchy indicate the type of component and the state, as shown in the following table.

Table 5-128. Design Hierarchy Icons

Icon	Description
	SmartDesign component
	SmartDesign component with HDL netlist not generated
	IP core was instantiated into SmartDesign but the HDL netlist is not generated
	Core
	Error during core validation
	Updated core available for download
	HDL netlist
	Shows ungenerated components
	Shows unknown modules
	Expands all the files and folders in the Design Hierarchy
	Collapses all the files and folders in the Design Hierarchy
	Finds the files in the Design Hierarchy

Linked Files with Relative Path in Design Hierarchy with Environment Variable

The following figure shows linked files that have a relative path in the design hierarchy with the Environment variable. Linked files that are in a drive different to the drive specified in Environment variable path are shown as absolute files in Windows.

Properties of file in Design Hierarchy shows Relative Path and Relative Path root directory

You can verify which bitstream file was programmed on the devices by running the VERIFY or VERIFY_DIGEST actions on each device that was programmed. This is a costly and time-consuming process. To speed up the verification process, digests are printed during bitstream generation and bitstream programming.

These digests can be compared to verify that all the devices were programmed with the correct bitstream file.

The bitstream file is divided into three major component sections: FPGA fabric, eNVM, and Security. A valid bitstream will contain a combination of any of the three primary bitstream components.

Use Case

When a customer creates a design in Libero and then exports the STAPL file (for FlashPro) or programming job (for FlashPro Express), the digest of each of the primary components is printed in the Libero log window and saved in a digest file under the export folder. The digest file is a text file containing the bitstream component name with its corresponding digest. The name of the digest file will match the name of the STAPL/programming job exported, and will be appended with a “.digest” extension. It also contains additional information about the design, such as Design Name, Checksum, Design Version, and Entire Bitstream Digest to help identify the design to which this digest file corresponds.

The customer then sends the STAPL/programming job to a production programming house. Now, when the devices are programmed, the digest of each of the primary components is printed in the log window. The production programming house saves the log files and sends the devices along with log files back to the customer. The customer can verify that the correct design was programmed on the device by matching the digests in the log file with *.digest file under the Libero export folder.

See Also

Export Bitstream

The Design Rules Check runs automatically when you generate your SmartDesign; the results appear in the Reports tab. You can also initiate a Design Rules Check by clicking on the

To view the results, from the Design menu, choose Reports.

• Status displays an icon to indicate if the message is an error or a warning (as shown in the following figure). Error messages are shown with a small red sign and warning messages with a yellow exclamation point.
  
• Message identifies the specific error/warning (see the following list); click any message to see where it appears on the Canvas.
• Details provides information related to the Message.

Message Types:

Unused Instance - You must remove this instance or connect at least one output pin to the rest of the design.

Out-of-date Instance - You must update the instance to reflect a change in the component referenced by this instance.

Undriven Pin - To correct the error you must connect the pin to a driver or change the state, that is, tie LOW (GND) or tie HIGH (VCC).

Floating Driver - You can mark the pin unused if it is not being used in the current design. Pins marked unused are ignored by the Design Rules Check.

Unconnected Bus Interface - You must connect this bus interface to a compatible port because it is required connection.

Required Bus Interface Connection – You must connect this bus interface before you can generate the design. These are typically silicon connection rules.

Exceeded Allowable Instances for Core – Some IP cores can only be instantiated a certain number of times for legal design because of silicon limitations. You must remove the extra instances.

Incompatible Family Configuration – The instance is not configured to work with this project’s Family setting. Either it is not supported by this family, or you need to re-instantiate the core.

Incompatible Die Configuration – The instance is not configured to work with this project’s Die setting. Either it is not supported or you need to reconfigure the Die configuration.

No RTL License, No Obfuscated License, No Evaluation License – You do not have the proper license to generate this core. Visit the Microchip Licensing page to obtain the necessary license.

No Top-level Ports - There are no ports on the top-level. To auto-connect top-level ports, right-click the Canvas and choose Auto-connect.

Self-Instantiation - A component cannot instantiate itself. This is reported only in the Log/Message Window.

The Constraints Editor enables you to add, edit, and delete.

To add a new constraint:

1. Select a constraint type from the constraint browser.
2. Enter the constraint values in the first row and click the green check mark to apply your changes. To cancel the changes, press the red cancel mark.
3. The new constraint is added to the Constraint List. The green syntax flag indicates that the constraint was successfully checked.

To edit a constraint:

1. Select a constraint type from the constraint browser.
2. Select the constraint, edit the values, and click the green check mark to apply your changes. To cancel the changes, press the red cancel mark. The green syntax flag indicates that the constraint was successfully checked.

To delete a constraint:

1. Select a constraint type from the constraint browser.
2. Right-click the constraint you want to delete and choose Delete Constraint.

The Files tab displays all the files associated with your project, listed in the directories in which they appear.

Right-clicking a file in the Files tab provides a menu of available options specific to the file type. You can delete files from the project and the disk by selecting Delete from the right-click menu.

You can instantiate a component by dragging the component to a SmartDesign Canvas or by selecting Instantiate in SmartDesign from the right-click menu. See the SmartDesign User Guide for more details.

You can configure a component by double-clicking the component or by selecting Open Component from the right-click menu.

File Types

When you create a new project in the Libero SoC it automatically creates new directories and project files. Your project directory contains all your 'local' project files. If you import files from outside your current project, the files must be copied into your local project folder (The Project Manager enables you to manage your files as you import them).

Depending on your project preferences and the Libero SoC version you installed, the software creates directories for your project.

The top-level directory (<project_name>) contains your PRJ file; only one PRJ file is enabled for each Libero SoC project.

• component directory - Stores your SmartDesign components (SDB and CXF files) for your Libero SoC project.
• constraint directory - All your constraint files (SDC, PDC).
• designer directory - *_ba.sdf, *_ba.v(hd), STP, TCL (used to run designer), designer.log (log file) hdl directory - all hdl sources. *.vhd if VHDL, *.v and *.h if Verilog, *.sv if SystemVerilog simulation directory - meminit.dat, modelsim.ini files.
• smartgen directory - GEN files and LOG files from generated cores.
• stimulus directory - BTIM and VHD stimulus files.
• synthesis directory - *.edn, *_syn.prj (Synplify log file), *.srr (Synplify log file), *.tcl (used to run synthesis) and many other files generated by the tools (not managed by Libero SoC).
• tooldata directory - includes the log file for your project with device details.

Anything that describes your design, or is needed to program the device, is a project source. These might include schematics, HDL files, simulation files, testbenches, and so on. Import these source files.

To import a file:

1. From the File menu, choose Import Files.
2. In Files of type, choose the file type.
3. In Look in, navigate to the drive/folder where the file is located.
4. Select the file to import and click Open.
   Note: You cannot import a Verilog File into a VHDL project and vice versa.

This is a generic error produced by the placer when it is unable to place a design. The most common cause for this failure is that the placer was unable to find a solution, which could fit the design into the chip, either because the design is close to maximum utilization, or logic cannot be fit into user-defined region constraints.

If Libero is unable to find a legal placement, a list of unplaced cells will be provided in the log. The cells in this list might not be the cause of the placement problem; it is quite possible that some other constrained block of logic was placed first and now prohibits further placement. However, starting with the unplaced cell list is the easiest and most likely course:

• The simplest potential solution is to remove all placement constraints of the unplaced cells, and re-run Place and Route.

However, the cells in this list might not be the cause of the placement problem; it is quite possible that some other constrained block of logic which was placed first and now prohibits further placement. If removing the placement constraints on the unplaced cells fails.

• Remove all region constraints and re-run Place and Route. Some designers make it a practice to put all their region constraints in a single, separate PDC file; in which case they need to disable that file.
  • If this Place and Route re-run still fails, there might be wider issues with the design's size and complexity that cannot be addressed by changes to Place and Route options.
  • If the unconstrained Place and Route re-run succeeds, then the you must add back constraints a few regions at a time in order of "simplicity". Usually, big regions with lots of free space are "simpler" for the placer, whereas tall/narrow regions with high utilization are "harder". Re-run Place and Route with each constraint restoration and repeat the process until the failing region(s) is identified.

    Depending on requirements, the failing region might be handled by removing or changing its constraints, or revising its design to use less resources.

You can also re-run the Placer in high-effort mode. Applying high-effort mode to a design which is very full can incur additional runtime and can produce a placement solution that might not meet tight timing constraints because the placer will aggressively attempt to fit the design. In practice, customers are encouraged to apply the previous suggestions first; and utilize high-effort mode only when other approaches are exhausted.

This design is very difficult to place, and high-effort techniques were required to fit it. This might lead to increased layout runtime and diminished timing performance.

This message typically appears in designs with high utilization — a very full design, or a design with region constraints which are, themselves, very full. It can also occur in designs with moderate utilization but with numerous, long carry chains.

No immediate action is required. However, if this notice is observed during Layout, the resultant performance of the design and the runtime of the Layout tools might not be optimal, and there is a strong possibility that reducing the size of the design, or relaxing region and floorplanning constraints, will help to improve timing closure and runtime.

The Save Project As dialog box enables you to save your entire project with a new name and location. To access this dialog box, choose Save Project As from the Project menu.

Project Name

Type the project name for your modified project.

Project Location

Accept the default location or Browse to the new location where you can save and store your project. All files for your project are saved in this directory.

Content

Copy links locally - Check this check box to copy the links from your current project into your new project. If you do not check this check box, the links will not be copied and you must add them manually.

Files

• All - Includes all your project and source files; the state of the project is retained.

• Project files only - Copies only the project-related information required to retain the state of the project.

• Source files only - Copies all the source files into the specified location. This means the configuration of all the tools in the tool chain is retained but the states are not. Source files means constraint information and component information available in the component, hdl and smartgen directories.

Files are saved as shown in the following table.

The Project Settings dialog box enables you to modify your Device, HDL, and Design Flow settings and your Simulation Options. In Libero SoC, from the Project menu, click Project Settings.

Device Selection

Sets the device Die and Package for your project. See the New Project Creation Wizard - Device Selection page for a detailed description of the options.

Device Settings

Default I/O Technology - Sets all your I/Os to a default value. You can change the values for individual I/Os in the I/O Attributes Editor.

System controller suspended mode. If the System controller suspended mode is enabled in any PolarFire design, the following operations will not be available during normal operation. For more information, refer to the System Services section in the PolarFire FPGA Security User Guide (UG0753).

• All System Controller services requested after power-up is complete and the System Controller is suspended
• System controller generated Tamper flags
• Device reset and zeroization Tamper responses
• SPI-Master In-Application Programming (IAP)
• SPI-Slave programming mode

For RT PolarFire devices, the System Controller suspended mode is enabled by default for all new RT PolarFire projects. If the System controller suspended mode is disabled, it increases vulnerability to radiation single event effects in the System controller.

Design Flow

See the Project Settings: Design flow for more information.

Analysis Operating Conditions

Sets the Operating Temperature Range, the Core Voltage Range, and Default I/O Voltage Range from the pick lists provided. Typical values are COM/IND/MIL; but others are sometimes defined.

Only EXT and IND ranges are available for PolarFire at present.

Once the "Range" value is set, the Minimum/Typical/Maximum values for the selected range are displayed.

These settings are propagated to Verify Timing, Verify Power, and Backannotated Netlist for you to perform Timing/Power Analysis.

Simulation Options and Simulation Libraries

Sets your simulation options. See the Project Settings: Simulation Options topic for more information.

This option facilitates the users to provide global include file/s in Libero and manage how these files are sent to downstream tools occurring in Design Flow process.

Libero GUI facilitates user to provide Global Include Files. On right clicking a file in Design Hierarchy view, user can either set a file as global include by selecting Set Global Include option or unset a file as global include by selecting Unset Global Include option.

Linked files can also be set as Global Include files. The files that are set are highlighted in Design hierarchy view as shown in the following figure.

The selected order of global include files is shown in Info tab in log window:

Info: Global Include file requires System Verilog setting to be in MFCU mode. Enabling Multi File Compilation Unit internally.

Once the core component is created and generated, the component related files like the generated HDL netlist file are also generated to the directory <project directory>/component/work/<component_name>. The generated HDL netlist file of the core component now contains the component description/configuration information in Tcl as comments. These comments also include Family Name and Part Number of the device used. The following figure shows a sample Tcl component description of the core COREAXI4INTERCONNECT.

Search options vary depending on your search type.

To find a file:

1. Use CTRL + F to open the Search window.
2. Enter the name or part of name of the object you wish to find in the Find field. '*' indicates a wildcard, and [*-*] indicates a range, such as if you search for a1, a2, ... a5 with the string a[1-5].
3. Set the Options for your search; options vary depending on your search type.
4. Click Find All (or Next if searching Text).

   Searching an open text file, Log window, or Reports highlights search results in the file itself. All other results appear in the Search Results window (as shown in the following figure).

Match case: Select to search for case-sensitive occurrences of a word or phrase. This limits the search so it only locates text that matches the upper- and lowercase characters you enter.

Match whole word: Select to match the whole word only.

Currently Open SmartDesign

Searches your open SmartDesign, returns results in the Search window.

Type: Choose Instance, Net or Pin to narrow your search.

Query: Query options vary according to Type.

Currently Open Text Editor

Design Hierarchy

Searches your Design Hierarchy; results appear in the Search window.

Find All: Displays all finds in the Search window.

Stimulus Hierarchy

Searches your Stimulus Hierarchy; results appear in the Search window.

Find All: Displays all finds in the Search window.

Log Window

Searches your Log window; results are highlighted in the Log window - they do not appear in the Search Results window.

Find All: Highlights all finds in the Log window.

Next: Proceed to next instance of found text.

Previous: Proceed to previous instance of found text.

Reports

Searches your Reports; returns results in the Reports window.

Find All: Highlights all finds in the Reports window.

Next: Proceed to next instance of found text.

Previous: Proceed to previous instance of found text.

Files

Searches your local project file names for the text in the Search field; returns results in the Search window.

Find All: Lists all search results in the Search window.

Files on disk

Searches the files' content in the specified directory and subdirectories for the text in the Search field; returns results in the Search window.

Find All: Lists all finds in the Search window.

File Type: Select a file type to limit your search to specific file extensions or choose *.* to search all file types.

The Organize Source Files dialog box enables you to set the source file order in the Libero SoC.

Click the Use list of files organized by User radio button to add/remove source files for the selected tool.

To specify the file order:

1. In the Design Flow window under Implement Design, right-click Synthesize and choose Organize Input Files > Organize Source Files. The Organize Source Files dialog box appears.
2. Click the Use list of files organized by User radio button to Add/Remove source files for the selected tool.
3. Select a file and click the add or remove buttons, as necessary. Use the Up and Down arrows to change the order of the Associated Source files.
4. Click OK.

SmartDesign testbench is a GUI-based tool that enables you to design your testbench hierarchy. Use SmartDesign testbench to instantiate and connect stimulus cores or modules to drive your design.

You can create a SmartDesign testbench by right-clicking a SmartDesign component in the Design Hierarchy and choosing Create Testbench > SmartDesign. SmartDesign testbench automatically instantiates the selected SmartDesign component into the Canvas. You can also double-click Create SmartDesign Testbench in the Design Flow window to add a new SmartDesign testbench to your project. New testbench files appear in the Stimulus Hierarchy. SmartDesign Testbench automatically instantiates your SmartDesign component into the Canvas.

You can instantiate your own stimulus HDL or simulation models into the SmartDesign Testbench Canvas and connect them to your DUT (design under test). You can also instantiate Simulation Cores from the Catalog. Simulation cores are simulation models (such as DDR memory simulation models) or basic cores that are useful for stimulus generation (such as Clock Generator, Pulse Generator, or Reset Generator). Click the Simulation Mode check box in the Catalog to view available simulation cores. Refer to the SmartDesign User Guide for more information.

To view the Stimulus Hierarchy, from the View menu choose Windows > Stimulus Hierarchy.

The Stimulus Hierarchy tab displays a hierarchical representation of the stimulus and simulation files in the project. The software continuously analyzes and updates files and content. The tab in the following figure displays the structure of the modules and component stimulus files as they relate to each other.

Expand the hierarchy to view stimulus and simulation files. Right-click an individual component and choose Show Module to view the module for only that component.

Select Components, instance or Modules from the Show drop-down list to change the display mode. The Components view displays the stimulus hierarchy; the modules view displays HDL modules and stimulus files.

The file name (the file that defines the module or component) appears in parentheses. Click Show Root Testbenches to view only the root-level testbenches in your design.

Right-click and choose Properties; the Properties dialog box displays the pathname, created date, and last modified date.

All integrated source editors are linked with the SoC software; if you modify a stimulus file the Stimulus Hierarchy automatically updates to reflect the change.

The following table shows the icons in the hierarchy indicate the type of component and the state.

Table 5-130. Design Hierarchy Icons

Icon	Description
	SmartDesign component
	SmartDesign component with HDL netlist not generated
	SmartDesign testbench
	SmartDesign testbench with HDL netlist not generated
	IP core was instantiated into SmartDesign but the HDL netlist has not been generated
	HDL netlist

Use timing exceptions to overwrite the default behavior of the design path. Timing exceptions include:

• Setting multicycle constraint to specify paths that (by design) will take more than one cycle.
• Setting a false path constraint to identify paths that must not be included in the timing analysis or the optimization flow.

• Setting a maximum/minimum delay constraint on specific paths to relax or to tighten the original clock constraint requirement.

This allows a way to use same set of tools and same vault location if Libero SoC is started from the same installed location. An admin (the person who generally takes care of Libero SoC installation) creates an admin profile. This profile is common to all Libero SoC users from the same installed location. Individual users do not need to have to create the tool profile and vault location.

To create an admin profile, start adminprofile.exe from <Libero installation directory>/Designer/bin location in case of windows and from <Libero installation directory>/bin64 location in case of Linux.

This admin profile will be common to all users who are using Libero SoC from the installed path, by providing the following values:

• Synplify location
• ModelSim ME Pro location
• Vault location
• Any other tool mentioned in admin profile utility

To create an admin profile, all the fields in the dialog box must be entered correctly. The vault location provided during admin profile creation will have precedence and will be used by all the other users.

Vaults and tools location

Vault location: Location of megavault consisting of all the cores for the current Libero SoC version must be mentioned.

Tools location: Correct tool executable location must be entered which is accessible by all of Libero SoC users.

Using admin profile, you can use Libero SoC-provided tools, which are a part of Libero SoC Design Suite, by selecting the Use the tool from Libero SoC Design Suite installation option. In this case, location of specific tools will be used from Libero SoC installation.

The Tool Profiles dialog box enables you to add, edit, or delete your project tool profiles.

Each Libero SoC project can have a different profile, enabling you to integrate different tools with different projects.

The following table shows the supported tool versions in this release.

To set or change your tool profile:

1. From the Project menu, choose Tool Profiles. Select the type of tool you wish to add.
   • To add a tool: Select the tool type and click the Add button. Fill out the tool profile and click OK.
   • To change a tool profile: After selecting the tool, click the Edit button to select another tool, change the tool name, or change the tool location.
   • To remove a tool from the project: After selecting a tool, click the Remove button.

   

2. When you are done, click OK.

The tool profile with the padlock icon indicates that it is a pre-defined tool profile (the default tool that comes with the Libero SoC Installation).

To export the tool profile and save it for future use, click the Export Tool Profiles dialog box and save the tool profile file as a tool profile *.ini file. The tool profile *.ini file can be imported into a Libero SoC project (File > Import > Others) and select Tool Profiles (*.ini) in the File Type pull-down list.

This dialog box allows you to set your personal preferences for how Libero SoC manages the design flow across the projects you create.

Constraint Flow

• Warn me when derived timing constraints generation override existing constraints (enhanced constraint flow):

  Libero SoC can generate/derive timing constraints for known hardware blocks and IPs such as SerDes, CCC. Check this box to have Libero SoC pop up a warning message when the generated timing constraints for these blocks override the timing constraints you set for these blocks. This box is checked by default.

Design Flow Rule Checks

• Warn me when Firmware applications must be recompiled because of hardware configuration changes.

  Check this box if you want Libero SoC to display a warning message. This box is checked by default.

• Warn me when I/Os are not all assigned and locked before programming data generation.

  I/Os must always be assigned and locked before programming data generation. Check this box if you want Libero SoC to display a warning message. This box is checked by default.

SmartDesign Generation Options

• Generate recursively

  In this mode, all sub-designs must be successfully generated before a parent can be generated. An attempt to generate a SmartDesign results in an automatic attempt to generate all sub-designs.

• Generate non-recursively

  In this mode, the generation of only explicitly selected SmartDesigns is attempted. The generation of a design can be marked as successful even if a subdesign is ungenerated (either never attempted or unsuccessful).

Libero tool generates a report listing all the IPs used in the design project.

The report consists of the following:

• Project Information
• List of components in the project with the following information:
  • Component name
  • Component State
  • IP Core (Vendor, Library, Name, Version) used to create the component
  • TCL Parameters of the core used to create the component
• Information of core instances used in the SmartDesign.
  • Component Name – In the form of "smartdesign_name>_<instance_name>"
  • Component State – State of the instance in the SmartDesign
  • Vendor, Library, Name, and Version of the core used to create the instance
  • TCL Parameters of the core used to create the instance
• Single Page SystemBuilder components
• Multi Page SystemBuilder components without parameter list of latest core versions available for the cores used in the project. This list is present at the end of an open project.

To export the IP CORE Usage Report, go to File > Export > IP Core Usage Report. When clicked, a file dialog box appears to navigate to the location and file format to save the report. The file can be generated in either “JSON” or “txt” format.

Once the report is generated successfully, the location to where the report is exported is shown in log window.

A global option to force update the design flow to Pass state is added to Libero SoC v12.5. The tool’s state is force updated to PASS state only for Synthesize/Compile and Place and Route tools. The remaining tools remain in the same state they were in before the force update action was performed.

To differentiate between PASS state and FORCE UPDATE PASS state, the following icon and tooltip for the FORCE UPDATE PASS state (force update action) is added.

After the tool states are force updated to PASS state from Out of Date Design state, the following message appears in the log window.

On running programming tool – Generate FPGA Array Data, a warning message pops up if Synthesize, Place and Route, or both are in the Force Update Pass state.

The log window shows the following message.

Libero tool generates hierarchical reports that show parameter/generic values used in instantiation of the modules. Report is generated for the active top module. Report will be generated for only that active top module which is not instantiated in any other modules. The report is generated in xml format.

In the following example, report will not be generated for the active root (top) module COREABC_C0 because it is instantiated in sd1. The file sd1 needs to be set as a root to generate the report.

The report can be generated by right clicking on the active top module and selecting Export Parameter Report option in Design Hierarchy window. Once the report is generated successfully, the location to where the report is exported is shown in log window.

Error message is flagged in cases where the user tries to generate report for a module that is instantiated in another module.

Error: Parameter/Generic report cannot be exported for a module that is instantiated in any other module. It can only be exported for top level modules. Set a top level module as the root or specify a top level module in the Tcl command ‘export_parameter_report’ to be able to export the report.

This feature supports absolute and relative path in batch mode for PolarFireSOC MSS Configurator.

pfsoc_mss.exe \
-CONFIGURATION_FILE:<path_to_file>/<file_name>.cfg \
-OUTPUT_DIR:<path_to_file>/MSS \
-EXPORT_HDL:false \
-LOGFILE:<path_to_file>/logfile.txt

D:/dir_1/dir_2/dir_3/pfsoc_mss.exe \
-CONFIGURATION_FILE:./soft/sqadir/user/mss_configuration.cfg \
-OUTPUT_DIR:d:./soft/sqadir/user/MSS \
-EXPORT_HDL:false \
-LOGFILE:/soft/sqadir/user//logfile.txt

D:/dir_1/dir_2/dir_3/pfsoc_mss.exe \
-CONFIGURATION_FILE:./../mss_configuration.cfg \
-OUTPUT_DIR:d:/MSS \
-EXPORT_HDL:false \
-LOGFILE:d:/logfile.txt

<current_working_directory>/../../mss_configuration.cfg

<current_working_directory>/MSS