3.1 Overview

Smart high-level synthesis (SmartHLS™) Compiler is an Eclipse-based integrated development environment that takes C++ software code as input and generates a SmartDesign IP component (Verilog HDL) as an output. Hardware engineers can instantiate the generated SmartDesign IP component in the SmartDesign Canvas available in Libero® SoC design suite to build an FPGA system.

SmartHLS automatically compiles a C/C++ program into hardware described in Verilog HDL (Hardware Description Language). The generated hardware can be programmed onto a Microchip® FPGA (Field-Programmable Gate Array). Hardware implemented on an FPGA can provide 2-10X performance and power benefits over the same computation running on regular processors.

SmartHLS includes C/C++ to Verilog high-level synthesis tool and is tested on Windows and Linux 64-bit operating systems.

The following table describes each document shipped with SmartHLS.

Document TitleDescription
Getting StartedInstallation and a quick start guide
User GuideHow to use SmartHLS™ to generate hardware
Optimization GuideHow to optimize the generated hardware
Hardware ArchitectureSynthesized hardware architecture
SmartHLS Pragmas ManualPragmas manual
Constraints ManualConstraints manual
License SetupHow to set up a license for SmartHLS
Supported FPGA DevicesSupported FPGA devices
Supported Libero® VersionSupported Libero version
Frequently Asked QuestionsFrequently asked questions
SmartHLS Migration GuideSmartHLS Migration Guide
Technical SupportHow to create tech support cases and post to our forum

For detailed training on using SmartHLS and example applications, see our GitHub Examples repository.

Note: This publication may include sensitive terms like master/slave. While Microchip strives to use inclusive language, certain terms are retained for technical reasons and backward compatibility. Microchip does not endorse these terms.