1.1 Libero SoC Design Suite v2025.2 Welcome Page

PolarFire, PolarFire SoC, RT PolarFire, and RT PolarFire SoC

• IOD TX Ratio 5, single-ended data output: Enhanced DRC to ensure that the N-side of the IOD pair is not available for use.
• Preferred clock input:
  • MPF500T/TS/TL/TLS, RTPF500T/TS/TL/TLS, RTPF500ZT/TS/TL/TLS:
    • Enabled the REF_CLK I/O from Transceiver QUAD4 of the device.
  • MPFS460T/TS/TL/TLS, RTPFS460ZT/TS/TL/TLS:
    • Enabled the REF_CLK I/O from Transceiver QUAD4 of the device.
  • MPFS025T/TS/TL/TLS
    • Enabled preferred clock input I/Os to the two PLLs at the SE corner.
  • Periphery placement: Implemented automatic assignment of DLL and PLL blocks when cascaded.
• PF_CCC: Updated DLL phase generation controls.

• SPI Flash Clients:
  • If the SPI bitstream client is not present, you can create SPI data storage clients at any address, including those below 0x400.
  • Inserted a Key Mode column to the SPI Flash Clients Table for encrypting the SPI file (default is Key/UEK1/UEK2).
• Serial Flash Memory:
  • Winbond W25Q64JV: Added STAPL file generation for FlashPro Express and SPI Flash memory support on FlashPro 6.
  • Micron MT25QL128ABA: Added STAPL file generation for FlashPro Express.
• Upgraded Synplify Pro ME and Identify tools to W-2025.03M-SP1-1.

PolarFire, RT PolarFire, PolarFire SoC and RT PolarFire SoC Enhancements

• Simulation model enhancements:
  • Aded post-layout back-annoted timing simulation of Differential input I/O.
  • Added simulation support for wide-mode programmable input delay taps in PF_IO and PF_IOD_GENERIC_RX cores.
• IOD Octal DDR:
  • Exposed PLL_POWERDOWN_N by default, to facilitate enabling of the PLL only when the REF_CLK input is stable.
  • Added DQS_DELAY_TAP options up to 139.
  • Added support for non-integer clock frequency entry.
  • Improved timing constraints generation for coverage.
  • Async-assert and Sync-deassert Reset: Improved performance by inserting two-stage pipeline and register duplication.
• IOD RX: Expose fractional clock parallel data enabled in Fractional Dynamic mode.
• SPACEWIRE_RX: Added option to expose Failsafe ODT_EN port.
• Design Initialization report: Inserted DLL register details.
• Dynamically delayed I/O interfaces (except DDR, LPDDR, QDR, CDR): IN_DELAY and OUT_DELAY options allowed in PDC to set the initial startup delay value, which can be dynamically tuned during operation.
• PF_SRAM_AHBL_AXI: Added new options for high reliability to enable fault tolerance logic, synchronous reset, and timeout counts for read and write operations on the AHBL or AXI interface.
• PF_SYSTEM_SERVICES: Added new options for high reliability to enable fault tolerance logic.
• CoreAXI4Interconnect, CoreAHB-Lite: Refreshed memory map definitions with the new initiator and target terminologies.
• SmartDebug Live Probe: Added support for trigger signal’s edge selection.
• MPF200T-FCG784: Upgraded to the Silver license.

RTG4 Enhancements

• RTG4_SRAM_AHBL_AXI: Added new options for high reliability to enable fault tolerance logic, synchronous reset, and timeout counts for read and write operations on the AHBL or AXI interface.

PolarFire SoC Standalone MSS Configurator

• Added new Physical Memory Protection (PMP) lockdown strategies:
  • Reorganized PMP interface layout for more efficient configuration.
  • Added Expert Mode to allow direct configuration of PMP register settings.
• DDR partition: Reorganized DDR memory partition settings to a dedicated tab.
• I²C voltage: Expanded MSS I/O to operate at 2.5V when used with I²C peripherals.
• CAN voltage: Expanded MSS I/O operation at 1.2V, 1.5V, 1.8V, and 2.5V to enable additional Low Voltage CMOS I/O standards for MSS CAN controller I/O connection to external CAN transceiver, where supported by user board design and transceiver specifications.
• QoS AXI Initiator and Processor BFM: A mss_cpu_core can access the non-cache region of MSS DDR through the M14 port of the AXI switch. To mimic the processor behavior during simulation, you can choose to enable either the BFM for the mss_cpu_core or a tiny QoS AXI Initiator.

SmartHLS

• New Diagnostic Reporting System: Transitioned to a modernized system for reporting error and warning messages. A comprehensive reference guide is currently in development to assist users with troubleshooting during the design process.
• Top-Level Function Rules: To ensure proper functionality, HLS top-level functions can only be invoked from software testbench code.
• Improved Type Casting: Implemented the explicit overloaded casting operators, (double) and (float), to enable more intuitive C-style casting from SmartHLS arbitrary precision fixed-point data types (hls::ap_{u}fixpt) to C primitive float and double types.
• Enhanced Stability: Addressed various bugs and improved general system stability to ensure a smoother experience.