20.2.2.3.2 DDR Memory

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This section describes the options available in the MSS Configurator > DDR Memory tab for configuring MSS DDR Controller. For information about the architecture and functional blocks of MSS DDR Controller, see PolarFire SoC MSS Technical Reference Manual .

The following table lists the available options on the DDR Memory tab.

Table 20-16. DDR Memory Tab
Option	Description
DDR Memory Type	Allows selection of the required DDR type from the pull-down. The following memory types are available: UNUSED DDR3 DDR3L DDR4 LPDDR3 LPDDR4 Based on the DDR Memory Type selection, the DDR configuration options available on the DDR Topology, DDR Controller, DDR Memory Initialization, and DDR Memory Timing tabs vary. All DDR parameters must be configured according to the data sheet from the DDR vendor.
Lock Down DDR I/Os	Locks all DDR-related I/O pins after configuration and prevents them from being reassigned to fabric logic or reconfigured by software after boot.
JEDEC Presets	Pre‑defined DDR configuration profiles provided in the MSS Configurator that automatically populate DDR parameters according to the JEDEC standard defaults for a selected memory type and speed grade. Changing the DDR memory type resets the available JEDEC presets.

DDR Topology

The DDR Topology tab controls the physical aspects of the memory, such as data and address widths, enabling of ECC and DM, and setting the clock frequency. The following image shows the DDR Topology tab when DDR4 memory type is selected.

The following table lists the available options on the DDR Topology tab.

Table 20-17. DDR Topology

Option

Description

DQ Width

Specifies the total data bus width of the DDR interface between the MSS DDR controller and the external memory devices. Supported values for all memory types are 16 and 32 bits. The default selection is 32 bits.

SDRAM Number of Ranks

Specifies how many independent SDRAM ranks are connected to the MSS DDR controller. A rank is a group of memory devices (logical memory array) that operate in parallel and share the data (DQ) and address buses, but are selected using a separate Chip Select (CS#) signal. Single (1) and dual (2) rank options are available. By default, single rank is selected.

This option is not available for LPDDR3 and LPDDR4 memory types, where only single rank is used.

Enable DM

Controls whether Data Mask (DM) signals are used on the DDR interface. DM pins allow the DDR controller to selectively mask (disable) individual byte lanes during write operations. Enabling DM is recommended when using the DDR3, DDR3L, and DDR4 memory types and for general-purpose systems and cached memory usages. By default, this option is enabled.

Enable Parity/Alert

This option is available only for DDR4 memory type. When selected, this option enables Command and Address (CA) parity checking on the DDR interface and activates the ALERT_n signal used by the SDRAM device to report parity errors and certain fault conditions.

Enable ECC

Enables Error Correcting Code (ECC) protection on the MSS DDR memory interface. When enabled, the MSS DDR controller implements Single-Error Correction, Double-Error Detection (SECDED) on data stored in external DDR memory.

ECC is implemented as 4 ECC bits per 32‑bit data, resulting in the following DDR bus widths:

x16 data → x18 total
x32 data → x36 total

When ECC is enabled, additional DQ_ECC pins are exposed which must be physically connected on the board.

This option is available only for DDR, DDR3L, and DDR4 memory types. When ECC is enabled, DM must be disabled.

Bank Group Address Width

Defines the number of bank-group address bits used by the DDR controller when accessing external SDRAM. This setting is only applicable to DDR4 memories and must match the organization of the DDR4 device used on the board. Supported values are 1 bit (2 bank groups) and 2 bits (4 bank groups). By default, 1 is selected.

Number of Clock Outputs

Specifies how many differential DDR clock pairs (CK/CK#) the MSS DDR controller drives to the external SDRAM devices. This must match how the DDR clock is physically routed on the board and how many memory devices or ranks require a clock.

This option is available for DDR3, DDR3L, and DDR4 memory types and only when dual rank is selected.

Memory Format

Describes the physical form factor and interconnection style of the DDR memory attached to the MSS DDR controller. The following memory formats are supported:

COMPONENT
UDIMM
RDIMM
LRDIMM
SODIMM

For DDR3, DDR3L and DDR4, the COMPONENT, UDIMM, RDIMM, LRDIMM, and SODIMM memory formats are supported. For LPDDR3 and LPDDR4, only the COMPONENT memory format is supported.

Enable address mirroring on odd ranks

Enables the MSS DDR controller to internally swap certain address and bank bits when accessing odd-numbered ranks (Rank 1, Rank 3, and so on). This compensates for a physical wiring convention used on multi‑rank DDR DIMMs, where the DRAM devices on odd ranks have some address pins intentionally crossed (mirrored).

This option is available only for DDR3, DDR3L, and DDR4 memory types when two or more ranks are used and the memory format configured is other than COMPONENT.

Row Address Width

Defines the number of row address bits the MSS DDR controller uses when accessing the external DDR memory. This value must match the value specified in the DDR memory device datasheet. The supported values are 12–16 (both inclusive).

Column Address Width

Defines how many column address bits the MSS DDR controller uses to select a column within an open row and bank in the DDR memory. This value must match the value specified in the DDR memory device datasheet. The supported values are 9–12 (both inclusive).

Bank Address Width

Defines how many address bits are used to select a bank (or bank group) inside the DDR memory device. This value is not editable and is derived from the DDR memory device datasheet. The supported values are as follows:

2 for DDR3, DDR3L, LPDDR3, and LPDDR4 memory types
3 for DDR4

Memory Clock Frequency (MHz)

Specifies the external DDR clock rate (CK/CK#) driven by the MSS DDR controller to the memory device. This value affects every DDR timing calculations. This value can be determined by considering the DDR memory device datasheet and fabric timing or clocking constraints. Note that the clock frequency is different from data rate. The following table lists the supported ranges.


Memory Type	Supported Values	Default Value
DDR3	~300–800 MHz	666
DDR3L	~300–800 MHz	666
DDR4	~400–1200 MHz	800
LPDDR3	~400–800 MHz	666
LPDDR4	~800–1600 MHz	800

DDR Controller

The following image shows the DDR Controller tab.

The following table lists the available options on the DDR Controller tab.

Table 20-18. DDR Controller
Option	Description
Drive	Drive settings control the output driver strength of the MSS DDR PHY pins. The values are presented in Ohms. The default and supported values vary for each memory type. The following settings are available: DQ Drive: Specifies the write data strength. DQS Drive: Specifies the write strobe strength. ADD/CMD Drive: Specifies the address and command strength. Clock Drive: Specifies the DDR clock strength.
ODT	On-Die Termination (ODT) for DQ and DQS signals. The values are presented in Ohms. The default and supported values vary for each memory type. The following settings are available: DQ ODT: ODT for data signals. ODT is always enabled on the receiving side of the DQ bus. DQS ODT: ODT for data strobe signals. Similar to DQ, termination is enabled on the receiving side.
Efficiency	Efficiency settings control the internal command scheduler of the DDR controller. They aim to reduce wasted cycles caused by unnecessary precharges, repeated row activations, and poor bank utilization. The following settings are available: Enable Activate/Precharge Look-Ahead: When enabled, the DDR controller looks ahead at pending memory requests and decides whether to keep a row open or precharge early to prepare for the next access. By default, this option is disabled. Address Ordering: Controls how system addresses are mapped to DDR field. The following options are available: Chip-Bank-Row-Col Chip-Row-Bank-Col (default)
ODT Activation Settings on Write/Read	These settings define which ODT pin(s) are asserted during write/read operations, per rank. In PolarFire SoC DDR, up to two ODT (ODT0 and ODT1) pins are supported. Each rank can be wired to ODT0, ODT1, or both. These options tell the controller which ranks enable ODT and when (note that ODT must be enabled on the receiving side to absorb reflections). These options are available only for DDR3, DDR3L, DDR4, and LPDDR3 memory types.
DQDQS Offset	DQDQS start training window offset: This option controls where the DDR controller begins searching for the valid timing window between DQ (data) and DQS (data strobe) during DQ–DQS training (read and/or write leveling). Values between 1–10 are supported. By default, this value is set to 1.
Reference Voltage	Reference Voltage (Vref) is the threshold voltage used by DDR receivers to decide whether a signal is a logic 0 or 1.These settings are available only for DDR4 and LPDDR4 memory types. The following settings are available: Vref CA (as % of bank VDDI): Reference voltage used by the DRAM to sample the Command/Address (CA) signals, expressed as a percentage of the DDR I/O bank supply voltage (VDDI). Vref data (as % of bank VDDI): Reference voltage used by the DRAM to sample the data signals, expressed as a percentage of the DDR I/O bank supply voltage (VDDI).
Initial CA Training CLK Offset	This setting defines the initial phase offset applied to the DDR clock when the controller starts CA (Command/Address) training. The following settings are available: Advanced CA training: Select this option to enable the CA training offset. Number of offsets: Specifies the required number of offsets. Up to 4 offsets can be enabled. Offset 0–Offset 3: Specifies the clock‑phase offset value in degrees.
CLK Push Order during Training	Specifies the order in which clock phase shifts are applied (pushed) during DDR training, mainly affecting CA clock training.

DDR Memory Initialization

The DDR Memory Initialization tab defines how the external DDR device itself is programmed during power‑up. Its main purpose is to configure the DDR mode registers so that the memory operates correctly and matches both the JEDEC specification and the specific DDR device used on the board.

In the PolarFire SoC architecture, these settings are executed by the E51 monitor core during boot as part of the automatic DDR bring‑up sequence.

The following figure shows the memory initialization configuration.

The following table describes the options available in the DDR Memory Initialization tab for DDR3 and DDR3L.

Table 20-19. DDR Memory Initialization for DDR3 and DDR3L
Category	Option	Description
Mode Register 0	Read Burst Type	Specifies how column addresses advance during a read burst. The following values are supported: Sequential (default): Data is returned from consecutive column addresses. For example, Col 0 → 1 → 2 → 3 and so on. Interleaved: Column addresses toggle in a predefined pattern around the starting address. Historically used to reduce bank conflicts in older systems.
	Burst Length	Defines how many data words are transferred per memory command. A data word is the width of the DDR interface (x16, x32, x64, and so on). The following values are supported: Fixed BL8 (default): 8 transfers. For example, for a x16 DRR, this means 16 bits × 8 transfers = 128 bits (16 bytes) per burst. On-the-fly BC4 or BL8: The memory device can dynamically select the burst length per command, instead of being fixed at initialization.
	Memory CAS Latency	Specifies the number of clock cycles between issuing a READ command and when the first data appears on the DQ pins. For example, if CAS latency is 5, data appears 5 memory clock cycles after READ. This value must match the DDR memory device datasheet.
Mode Register 1	ODT Rtt Nominal Value	Sets the internal termination resistance inside the DDR memory device which helps in reducing the signal reflections on the DQ/DQs lines. The values are defined relative to RZQ, an external precision resistor (~ 240 Ω) connected to the DRAM. The following values are supported: ODT Disabled (default): No ODT RZQ/2: ~ 120Ω RZQ/4: ~ 60Ω RZQ/6: ~ 40Ω RZQ/12 for non-write: ~ 20Ω RZQ/8 for non-write: ~ 30Ω
	Memory Additive CAS Latency	Adds extra latency between an ACTIVATE command and a READ/WRITE. The following values are supported: Disabled (default) CL-1: Adds a CAS latency of 1 clock cycle CL-2: Adds a CAS latency of 2 clock cycles
	Output Drive Strength	Controls the output driver impedance of the DDR memory device. The following values are supported: RZQ/6 (default): ~ 34Ω RZQ/7: ~ 40Ω
Mode Register 2	Self Refresh Temperature	Selects the temperature range assumed by the DRAM during self‑refresh. The following values are supported: Normal (default): Standard commercial temperature range. Suitable for most systems. Extended: High-temperature operation (industrial/automotive). Suitable for systems that may exceed normal operating temperatures.
	Memory Write CAS Latency	Specifies the number of clock cycles between a WRITE command and when write data is captured by the DRAM. Values between 5 and 12 are supported.
	Partial Array Self Refresh	Specifies how much of the DRAM array is refreshed during self-refresh mode and helps reduce self-refresh power consumption. Unrefreshed regions lose data. The following values are supported: Full (default) Half Quarter 1/8 Half (reversed) Quarter (reversed) 1/8 (reversed)
	Dynamic ODT (Rtt_WR)	Controls the ODT used only during WRITE operations. Enabling this option temporarily overrides Rtt_Nom (MR1) during write bursts. The following values are supported: Dynamic ODT Off (default) RZQ/4 (~60Ω) RZQ/2 (~120Ω)

The following table describes the options available in the DDR Memory Initialization tab for DDR4.

Table 20-20. DDR Memory Initialization for DDR4
Category	Option	Description
Mode Register 0	Read Burst Type	Specifies how column addresses advance during a read burst. The following values are supported: Sequential (default): Data is returned from consecutive column addresses. For example, Col 0 → 1 → 2 → 3 and so on. Interleaved: Column addresses toggle in a predefined pattern around the starting address. Historically used to reduce bank conflicts in older systems.
	Burst Length	Defines how many data words are transferred per memory command. A data word is the width of the DDR interface (x16, x32, x64, and so on). The following values are supported: Fixed BL8 (default): 8 transfers. For example, for a x16 DRR, this means 16 bits × 8 transfers = 128 bits (16 bytes) per burst. On-the-fly BC4 or BL8: The memory device can dynamically select the burst length per command, instead of being fixed at initialization.
	Memory CAS Latency	Specifies the number of clock cycles between issuing a READ command and when the first data appears on the DQ pins. For example, if CAS latency is 5, data appears 5 memory clock cycles after READ. This value must match the DDR memory device datasheet.
Mode Register 1	ODT Rtt Nominal Value	Sets the internal termination resistance inside the DDR memory device which helps in reducing the signal reflections on the DQ/DQs lines. The values are defined relative to RZQ, an external precision resistor (~ 240Ω) connected to the DRAM. The following values are supported: ODT Disabled: No ODT RZQ/2: ~ 120Ω RZQ/4 (default): ~ 60Ω RZQ/6: ~ 40Ω RZQ/12 for non-write: ~ 20Ω RZQ/8 for non-write: ~ 30Ω
	Memory Additive CAS Latency	Adds extra latency between an ACTIVATE command and a READ/WRITE. The following values are supported: Disabled (default) CL-1: Adds a CAS latency of 1 clock cycle CL-2: Adds a CAS latency of 2 clock cycles
	Output Drive Strength	Controls the output driver impedance of the DDR memory device. The following values are supported: RZQ/7 (default): ~ 34Ω RZQ/5: ~ 48Ω
Mode Register 2	Low Power Auto Self Refresh	Enables minimizing power consumption while preserving data when the system is idle or in a low‑power state. The following values are supported: Automatic (default) Manual–Normal Manual–Reduced Manual–Extended
	Memory Write CAS Latency	Specifies the number of clock cycles between the WRITE command and the moment when valid write data must be presented on the DQ bus. Values between 9–20 are supported.
	Dynamic ODT (Rtt_WR)	Controls the On‑die termination used only during WRITE operations. Enabling this option temporarily overrides Rtt_Nom (MR1) during write bursts. The following values are supported: Dynamic ODT Off (default) RZQ/2 (~120 Ω) RZQ/1 (~240 Ω) High-Z RZQ/3 (~80 Ω)
Mode Register 3	Fine Granularity Refresh Mode	Enables the memory to change how often refresh operations occur, trading refresh frequency against refresh latency and bandwidth impact. The following values are supported: Normal (1x): Standard JEDEC refresh Fixed 2x (default) Fixed 4x On-the-fly 1x/2x On-the-fly 2x/4x
Mode Register 4	Temperature Refresh Range	Defines the temperature operating range assumed by the DDR4 device for determining its required refresh rate. This setting tells the memory whether it should use normal or extended temperature refresh timing, as defined by the JEDEC specification. The following values are supported: Normal (default) Extended
	Temperature Refresh Mode	Controls whether the device actively monitors its internal temperature and automatically adjusts the refresh rate based on that temperature. This feature enables temperature‑controlled refresh, as defined by the JEDEC specification. The following values are supported: Disabled (default) Enabled
	Internal VRef Monitor	Specifies whether the device monitors its internally generated reference voltage (Vref) used by the input receivers for data (DQ), data strobes (DQS), and command/address signals. When the Internal Vref Monitor is enabled, the device continuously checks that its internal Vref generator remains within JEDEC‑specified limits. If the internal Vref drifts outside the allowed range due to voltage, temperature, or noise issues, the device can internally flag this condition (device-specific behavior). The following values are supported: Disabled (default) Enabled
	Self Refresh Abort Mode	Controls how the DDR4 device exits Self‑Refresh mode when normal operation must resume. Specifically, it determines whether the memory allows an early termination (abort) of an ongoing self‑refresh cycle. The following values are supported: Disabled (default) Enabled
	READ Preamble	Configures the length of the DQS preamble that precedes valid read data when the device drives data back to the controller. This setting affects read timing margin, training robustness, and read latency. The following values are supported: 1 CK (default): One clock‑cycle DQS preamble 2 CK: Two clock‑cycle DQS preamble
	Write Preamble	Configures the length of the DQS preamble that the memory controller drives before write data is transferred to the device. It affects write timing margin, write leveling robustness, and write latency. The following value is currently supported: 1 CK (default): One clock‑cycle DQS preamble
Mode Register 5	CA Parity Latency Mode	Specifies the number of clock cycles the device waits before executing the command, allowing time for parity validation. The following values are supported: Disabled (default) 4 clocks 5 clocks 6 clocks 8 clocks
	ODT Input Buffer for Power-down	Controls whether the ODT input buffer remains enabled or is disabled when the device enters Power‑down mode. This setting affects power consumption, signal integrity, and bus stability during low‑power states. The following values are supported: Disabled (default) Enabled
	Parked ODT Value (Rtt_Park)	Defines the ODT resistance that the device applies when it is not actively participating in a read or write operation–that is, when the rank is idle (parked). This setting is mainly used in multi-rank DDR4 systems to maintain good signal integrity on the data bus. The following values are supported: Disabled (default) RZQ/4 RZQ/2 RZQ/6 RZQ/1 RZQ/5 RZQ/3 RZQ/7
Mode Register 6	Vref Calibration Enable	Controls whether the device participates in VrefDQ calibration (Vref training) during memory initialization. This feature allows the controller to optimize the data input reference voltage (VrefDQ) to improve read and write reliability. The following values are supported: Enabled (default) Disabled
	Vref Calibration Range	Defines the allowed voltage search window that the device uses during VrefDQ calibration (Vref training). It limits the range of reference voltages the controller can sweep while determining the optimal DQ reference voltage (VrefDQ). The following values are supported: Range 1 (60%–92.5%) Range 2 (45%–77.5%)
	Vref Calibration Value	Specifies the exact reference voltage (VrefDQ) that the device uses for DQ/DQS input sampling when Vref calibration is disabled, or it defines the initial/final programmed value when calibration is enabled. This value affects read and write data reliability, because it sets the voltage threshold used to interpret logic levels on the data bus.

The following table provides the DDR Memory Initialization options for LPDDR3.

Table 20-21. DDR Memory Initialization for LPDDR3
Category	Option	Description
Mode Register 2	Data Latency (#RL, #WL)	Defines how many clock cycles elapse between a memory command and when valid data is transferred on the DQ bus. #RL (Read Latency) = CAS Latency + Additive Latency #WL (Write Latency) = CAS Write Latency + Additive Latency
Mode Register 3	Output Drive Strength	Configures the output driver impedance for data (DQ), data strobe (DQS), and, in some cases, command/address signals. This setting affects signal integrity, edge rate, EMI, and power consumption on the interface.
Mode Register 11	DQ ODT	Defines whether and how termination is applied on the DQ/DQS lines when the memory is actively driving or receiving data. The following values are supported: Disabled (default) RZQ/4 RZQ/2 RZQ/1
Mode Register 11	Power Down ODT	Controls whether ODT remains active or inactive when the device enters Power-down mode. This option affects standby power consumption and data bus stability while the memory is in a low-power state.

The following table provides the DDR Memory Initialization options for LPDDR4.

Table 20-22. DDR Memory Initialization for LPDDR4
Category	Option	Description
Mode Register 1	RD Pre-amble Type	Defines the DQS behavior immediately before read data starts. This setting affects how early the controller can detect and align to DQS. The following values are supported: Static (default): DQS is held at a constant logic level (0 or 1) before toggling. Toggle: DQS toggles for 1 UI before read data.
Mode Register 1	RD Post-amble Length	Determines how long DQS continues toggling after the last read data beat. The following values are supported: 0.5tCK (default): DQS toggles for half a clock cycle after last data. 1.5 tCK: DQS toggles for one and half a clock cycles after last data.
Mode Register 2	Read Latency (#RL, #nRTP)	Specifies the number of memory clock cycles between issuing a READ command and when the first valid read data appears on the DQ bus. It is represented as a combination of #RL (Read Latency) and #nRTP (Read‑to‑Precharge Time).
Mode Register 2	Write Latency	Specifies the number of clock cycles between issuing a WRITE command and when the DRAM expects valid write data. #WL (Write Latency) = CAS Write Latency + Additive Latency
Mode Register 3	Pull-up Calibration Point	Selects the reference point used to calibrate the pull-up (PMOS) output driver impedance of the device. The following values are supported: Mid-point (default) End-point
	WR Post-amble Length	Controls the length of the write post-amble, that is, how long DQS remains active after the last write data beat. The following values are supported: 0.5 tCK (default) 1.5 tCK
	Pull-down Drive Strength	Selects the pull-down (NMOS) output driver impedance for DQ/DQS signals. The following values are supported: RZQ/1 RZQ/2 (default) RZQ/3 RZQ/4
Mode Register 4	Self Refresh Abort Mode	Controls how the DDR4 device exits Self-Refresh mode when normal operation must resume. Specifically, it determines whether the memory allows an early termination (abort) of an ongoing self-refresh cycle. The following values are supported: Disabled (default) Enabled
Mode Register 11	DQ ODT	Selects the ODT resistance inside the LPDDR4 DRAM for data signals during read/write operations. The following values are supported: Disable 40Ω 48Ω 60Ω (default) 80Ω 120Ω 240Ω
Mode Register 11	CA ODT	Selects the ODT resistance inside the LPDDR4 DRAM for command/address signals. The following values are supported: Disable 40Ω 48Ω 60Ω (default) 80Ω 120Ω 240Ω
Mode Register 14	Vref Calibration Enable	Controls whether the device participates in VrefDQ calibration (Vref training) during memory initialization. This feature allows the controller to optimize the data input reference voltage (VrefDQ) to improve read and write reliability. The following values are supported: Enabled (default) Disabled
	Vref Calibration Range	Defines the allowed voltage search window that the device uses during VrefDQ calibration (Vref training). It limits the range of reference voltages the controller can sweep while determining the optimal DQ reference voltage (VrefDQ). The following values are supported: Range 1 (60%–92.5%) Range 2 (45%–77.5%)
	Vref Calibration Value	Specifies the exact reference voltage (VrefDQ) that the device uses for DQ/DQS input sampling when Vref calibration is disabled, or it defines the initial/final programmed value when calibration is enabled. This value affects read and write data reliability, because it sets the voltage threshold used to interpret logic levels on the data bus.
Mode Register 22	SoC ODT	Enables or disables the SoC ODT mode in the device. When enabled, the DRAM applies ODT during SoC-driven transactions. The following values are supported: Disable Enable (default)
	ODTE-CK	Enables Clock (CK) signal to assert SoC ODT when toggling. This option is selected by default.
	ODTE-CS	Enables Chip Select (CS) to assert SoC ODT. This option is selected by default.
	ODTE-CA	Enables Command/Address (CA) signals to assert SoC ODT. This option is selected by default.

DDR Memory Timing

The DDR Memory Timing tab controls the timing parameters, which are translated to the appropriate configuration values for the DDR subsystem IP.

Note:

All parameters are editable numeric fields.
All parameters support the JEDEC ranges.
The default values are auto‑computed when:
- Memory type is selected
- Frequency is changed
- Defaults are restored

The following image shows the DDR Memory Timing tab.

The following table describes the options available on the DDR Memory Timing tab that are applicable to DDR3 and DDR3L memory types.

Table 20-23. Timing Parameters for DDR3 and DDR3L
Category	Parameter	Description
Timing parameters dependent on speed bin	tRAS (ns)	Row Active Time Minimum time a row must remain open after an ACTIVATE command.
	tRCD (ns)	RAS to CAS Delay Delay from ACTIVATE (row open) to READ or WRITE command.
	tRP (ns)	Row Precharge Time Minimum time required to close (precharge) a row before opening another.
	tRC (ns)	Row cycle time Minimum time between ACTIVATE commands to the same bank. tRC = tRAS + tRP
	tWR (ns)	Write Recovery Time Minimum time from WRITE command to PRECHARGE.
	tFAW (ns)	Four ACTIVATE window Time window limiting how many ACTIVATE commands can occur.
Timing parameters dependent on speed bin and clock frequency	tWTR (cycles)	WRITE to READ delay Delay from WRITE command to a subsequent READ command.
	tRRD (ns)	Row to Row Delay Minimum time between ACTIVATE commands to different banks.
	tRTP (ns)	READ to PRECHARGE delay Minimum time from READ command to PRECHARGE.
Timing parameters dependent on operating condition	tREFI (ns)	Refresh interval Average time between refresh commands.
Timing parameters dependent on speed bin and page size	tRFC (ns)	Refresh cycle time Time required to complete a refresh operation.
Other timing parameters	tZQinit (cycles)	ZQ Initialization Time Time required for initial ZQ calibration after reset.
	ZQ Calibration Type	Selects the type of ZQ calibration performed. Long—full calibration Short—periodic fine calibration
	tZQCS (cycles)	ZQ Calibration Short Duration of a short (incremental) ZQ calibration.
	tZQoper (cycles)	ZQ Operation Time Minimum time between ZQ calibration commands.
	Enable User ZQ Calibration Controls	Allows manual control of ZQ timing parameters. When enabled, the user can override auto‑calculated ZQ values.
	Automatic ZQ Calibration Period (us)	Interval at which automatic ZQ short calibration is performed.

The following table lists and describes the timing parameters available for DDR4.

Table 20-24. Timing Parameters for DDR4
Category	Parameter	Description
Timing parameters dependent on speed bin	tRAS (ns)	Row Active Time Minimum time a row must remain open after an ACTIVATE command.
	tRCD (ns)	RAS to CAS Delay Delay from ACTIVATE (row open) to READ or WRITE command.
	tRP (ns)	Row Precharge Time Minimum time required to close (precharge) a row before opening another.
	tRC (ns)	Row cycle time Minimum time between ACTIVATE commands to the same bank. tRC = tRAS + tRP
	tWR (ns)	Write Recovery Time Minimum time from WRITE command to PRECHARGE.
	tCCD_L (cycles)	Long Column-to-Column Delay Minimum delay between two column commands (READ or WRITE) issued to banks in different bank groups.
	tCCD_S (cycles)	Short Column-to-Column Delay Minimum delay between two column commands (READ or WRITE) issued to banks within the same bank group.
Timing parameters dependent on operating condition	tREFI (us)	Refresh interval Average time between refresh commands.
Timing parameters dependent on speed bin and page size	tRFC (ns)	Refresh cycle time Time required to complete a refresh operation.
	tFAW (ns)	Four Activate Window Rolling time window during which no more than four ACTIVATE (ACT) commands are allowed.
Timing parameters dependent on speed bin and clock frequency	tWTR_L (cycles)	Long Write-to-Read Delay Minimum delay between a WRITE command and a subsequent READ command issued to a bank in a different bank group.
	tWTR_S (cycles)	Short Write-to-Read Delay Minimum delay between a WRITE command and a subsequent READ command issued to a bank in the same bank group.
	tRRD_L (cycles)	Long Row-to-Row Delay Minimum delay between two ACTIVATE (ACT) commands issued to banks in different bank groups.
	tRRD_S (cycles)	Short Row-to-Row Delay Minimum delay between two ACTIVATE (ACT) commands issued to different banks within the same bank group.
	tRTP (ns)	READ to PRECHARGE delay Minimum time from READ command to PRECHARGE.
Other timing parameters	tZQinit (cycles)	ZQ Initialization Time Time required for initial ZQ calibration after reset.
	ZQ Calibration Type	Selects the type of ZQ calibration performed. Long—full calibration Short—periodic fine calibration
	tZQCS (cycles)	ZQ Calibration Short Duration of a short (incremental) ZQ calibration.
	tZQoper (cycles)	ZQ Operation Time Minimum time between ZQ calibration commands.
	Enable User ZQ Calibration Controls	Allows manual control of ZQ timing parameters. When enabled, the user can override auto‑calculated ZQ values.
	Automatic ZQ Calibration Period (us)	Interval at which automatic ZQ short calibration is performed.

The following table lists and describes the timing parameters for LPDDR3

Table 20-25. Timing Parameters for LPDDR3
Category	Parameter	Description
Timing parameters dependent on speed bin	tRAS (ns)	Row Active Time Minimum time a row must remain open after an ACTIVATE command.
	tRCD (ns)	RAS to CAS Delay Delay from ACTIVATE (row open) to READ or WRITE command.
	tRP (ns)	Row Precharge Time Minimum time required to close (precharge) a row before opening another.
	tRC (ns)	Row cycle time Minimum time between ACTIVATE commands to the same bank. tRC = tRAS + tRP
	tWR (ns)	Write Recovery Time Minimum time from WRITE command to PRECHARGE.
	tFAW (ns)	Four ACTIVATE window Time window limiting how many ACTIVATE commands can occur.
	tMMR (cycles)	Mode Register to Mode Register Delay Minimum delay between two consecutive Mode Register commands.
	tMRW (cycles)	Mode Register Write Time Minimum time required to complete a Mode Register Write (MRW) command.
Timing parameters dependent on speed bin and clock frequency	tWTR (cycles)	WRITE to READ delay Delay from WRITE command to a subsequent READ command.
	tRRD (ns)	Row to Row Delay Minimum time between ACTIVATE commands to different banks.
	tRTP (ns)	READ to PRECHARGE delay Minimum time from READ command to PRECHARGE.
Timing Parameters dependent on operating condition	tREFI (ns)	Refresh interval Average time between refresh commands.
Timing parameters dependent on speed bin and page size	tRFC (ns)	Refresh cycle time Time required to complete a refresh operation.
Other timing parameters	tZQinit (us)	ZQ Initialization Time Time required for initial ZQ calibration after reset.
	ZQ Calibration Type	Selects the type of ZQ calibration performed. Long—full calibration Short—periodic fine calibration
	tZQCS (ns)	ZQ Calibration Short Time Time required to complete a short ZQ calibration (ZQCS command).
	tZQCL (ns)	ZQ Calibration Long Time Time required to complete a long ZQ calibration (ZQCL command).
	tZQRESET (ns)	ZQ Reset Time Minimum time the device must wait after a ZQRESET event before any ZQ calibration command (ZQCL or ZQCS) can be issued.
	Enable User ZQ Calibration Controls	Allows manual control of ZQ timing parameters. When enabled, the user can override auto‑calculated ZQ values.
	Automatic ZQ Calibration Period (us)	Interval at which automatic ZQ short calibration is performed.

The following parameters are supported for LPDDR4.

Table 20-26. Timing Parameters for LPDDR4
Category	Parameter	Description
Timing parameters dependent on speed bin	tRAS (ns)	Row Active Time Minimum time a row must remain open after an ACTIVATE command.
	tRCD (ns)	RAS to CAS Delay Delay from ACTIVATE (row open) to READ or WRITE command.
	tRP (ns)	Row Precharge Time Minimum time required to close (precharge) a row before opening another.
	tRC (ns)	Row cycle time Minimum time between ACTIVATE commands to the same bank. tRC = tRAS + tRP
	tWR (ns)	Write Recovery Time Minimum time from WRITE command to PRECHARGE.
	tMMR (cycles)	Mode Register to Mode Register Delay Minimum delay between two consecutive Mode Register commands.
	tMRW (cycles)	Mode Register Write Time Minimum time required to complete a Mode Register Write (MRW) command.
Timing parameters dependent on speed bin and clock frequency	tWTR (cycles)	WRITE to READ delay Delay from WRITE command to a subsequent READ command.
	tRRD (ns)	Row to Row Delay Minimum time between ACTIVATE commands to different banks.
	tRTP (ns)	READ to PRECHARGE delay Minimum time from READ command to PRECHARGE.
Timing Parameters dependent on operating condition	tREFI (ns)	Refresh interval Average time between refresh commands.
Timing parameters dependent on speed bin and page size	tRFC (ns)	Refresh cycle time Time required to complete a refresh operation.
Timing parameters dependent on speed bin and page size	tFAW (ns)	Four ACTIVATE window Time window limiting how many ACTIVATE commands can occur.
Other timing parameters	ZQ Calibration Time (us)	Defines how long the DDR controller waits for the ZQ calibration (ZQCL or ZQCS) to complete before resuming normal memory traffic.
	ZQ Calibration Latch Time (ns)	Minimum time required for the DRAM to latch (capture and apply) the results of a ZQ calibration operation after the calibration measurement itself has completed.
	tZQRESET (ns)	ZQ Reset Time Minimum time the device must wait after a ZQRESET event before any ZQ calibration command (ZQCL or ZQCS) can be issued.
	Enable User ZQ Calibration Controls	Allows manual control of ZQ timing parameters. When enabled, the user can override auto-calculated ZQ values.
	Automatic ZQ Calibration Period (us)	Interval at which automatic ZQ short calibration is performed.

Advanced

Available only for the LPDDR3 and LPDDR4 memory types, the Advanced tab controls the self refresh mode parameters (idle time to self refresh and clock disable in self refresh).

Table 20-27. Advanced options
Category	Option	Description
Self Refresh Mode	Enable DDR Self Refresh	Allows the DDR controller to place the external DRAM into Self‑Refresh mode, where the memory refreshes itself internally without requiring periodic refresh commands from the controller. This option is disabled by default.
	Idle time to self refresh (ms)	Minimum continuous idle duration after which the DDR controller will automatically place the DRAM into Self‑Refresh mode.
	CLK disable in Self Refresh	Controls whether the external DDR clock (CK) is stopped (disabled) while the DRAM is in Self‑Refresh mode. This option is disabled by default.