10.12.2 PCON0
| Name: | PCON0 |
| Offset: | 0x018E |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STKOVF | STKUNF | RWDT | RMCLR | RI | POR | BOR | |||
| Access | R/W/HS | R/W/HS | R/W/HC | R/W/HC | R/W/HC | R/W/HC | R/W/HC | ||
| Reset | 0 | 0 | 1 | 1 | 1 | 0 | q |
Bit 7 – STKOVF Stack Overflow Flag
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | A Stack
Overflow occurred (more CALLs than fit on the
stack) |
| 0 | A Stack
Overflow has not occurred or set to ‘0’ by
firmware |
Bit 6 – STKUNF Stack Underflow Flag
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | A Stack
Underflow occurred (more RETURNs than
CALLs) |
| 0 | A Stack
Underflow has not occurred or set to ‘0’ by
firmware |
Bit 4 – RWDT WDT Reset Flag
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | A WDT
Overflow/Time-out Reset has not occurred or set to ‘1’ by
firmware |
| 0 | A WDT
Overflow/Time-out Reset has occurred (set to ‘0’ in hardware when
a WDT Reset occurs) |
Bit 3 – RMCLR MCLR Reset Flag
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | A
MCLR Reset has not occurred or set to
‘1’ by firmware |
| 0 | A
MCLR Reset has occurred (set to ‘0’
in hardware when a MCLR Reset
occurs) |
Bit 2 – RI
RESET Instruction Flag
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | A
RESET instruction has not been executed or set to
‘1’ by firmware |
| 0 | A
RESET instruction has been executed (set to
‘0’ in hardware upon executing a RESET
instruction) |
Bit 1 – POR Power-on Reset Status
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | No Power-on
Reset occurred or set to ‘1’ by
firmware |
| 0 | A Power-on
Reset occurred (set to ‘0’ in hardware when a Power-on Reset
occurs) |
Bit 0 – BOR Brown-out Reset Status
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | No Brown-out
Reset occurred or set to ‘1’ by
firmware |
| 0 | A Brown-out
Reset occurred (set to ‘0’ in hardware when a Brown-out Reset
occurs) |