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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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Product Pages
SAM9X60
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8
Connectivity Subsystem
8.3
Flexible Serial Communication Controller (FLEXCOM)
8.3.8
SPI Functional Description
8.3.8.6
SPI FIFOs
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
8.1
Overview
8.2
Ethernet MAC 10/100 (EMAC)
8.3
Flexible Serial Communication Controller (FLEXCOM)
8.3.1
Description
8.3.2
Embedded Characteristics
8.3.3
Block Diagram
8.3.4
I/O Lines Description
8.3.5
Product Dependencies
8.3.6
Register Accesses
8.3.7
USART Functional Description
8.3.8
SPI Functional Description
8.3.8.1
Modes of Operation
8.3.8.2
Data Transfer
8.3.8.3
Host Mode Operations
8.3.8.4
SPI Client Mode
8.3.8.5
SPI Comparison Function on Received Character
8.3.8.6
SPI FIFOs
8.3.8.6.1
Overview
8.3.8.6.2
Sending Data with FIFO Enabled
8.3.8.6.3
Receiving Data with FIFO Enabled
8.3.8.6.4
Clearing/Flushing FIFOs
8.3.8.6.5
TXEMPTY, TDRE and RDRF Behavior
8.3.8.6.6
SPI Single Data Access
8.3.8.6.7
SPI Multiple Data Access
8.3.8.6.8
FIFO Overflow/Underflow Error
8.3.8.6.9
FIFO Thresholds
8.3.8.6.10
FIFO Flags
8.3.8.7
SPI Register Write Protection
8.3.8.8
Local Loopback Test Mode
8.3.9
TWI Functional Description
8.3.10
Register Summary
8.4
Quad Serial Peripheral Interface (QSPI)
8.5
Secure Digital MultiMedia Card Controller (SDMMC)
8.6
Controller Area Network (CAN)
8.7
Timer Counter (TC)
8.8
Pulse Width Modulation Controller (PWM)
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
8.3.8.6 SPI FIFOs
