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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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SAM9X60
Home
5
Image Subsystem
5.2
LCD Controller (LCDC)
5.2.6
Functional Description
5.2.6.1
Timing Engine Configuration
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
5.1
Overview
5.2
LCD Controller (LCDC)
5.2.1
Description
5.2.2
Embedded Characteristics
5.2.3
Block Diagram
5.2.4
I/O Lines Description
5.2.5
Product Dependencies
5.2.6
Functional Description
5.2.6.1
Timing Engine Configuration
5.2.6.1.1
Pixel Clock Period Configuration
5.2.6.1.2
Horizontal and Vertical Synchronization Configuration
5.2.6.1.3
Timing Engine Powerup Software Operation
5.2.6.1.4
Timing Engine Powerdown Software Operation
5.2.6.2
DMA Software Operations
5.2.6.3
Overlay Software Configuration
5.2.6.4
RGB Frame Buffer Memory Bitmap
5.2.6.5
YUV Frame Buffer Memory Mapping
5.2.6.6
Chrominance Upsampling Unit
5.2.6.7
Line and Pixel Striding
5.2.6.8
Color Space Conversion Unit
5.2.6.9
Two-Dimension Scaler
5.2.6.10
Color Combine Unit
5.2.6.11
LCDC PWM Controller
5.2.6.12
LCD Overall Performance
5.2.6.13
Input FIFO
5.2.6.14
Output FIFO
5.2.6.15
Output Timing Generation
5.2.6.16
Output Format
5.2.7
Register Summary
5.3
2D Graphics Engine (GFX2D)
5.4
Image Sensor Interface (ISI)
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
5.2.6.1 Timing Engine Configuration
