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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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SAM9X60
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6
Audio Subsystem
6.3
Inter-IC Sound Multi-Channel Controller (I2SMCC)
6.3.6
Functional Description
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
6.1
Overview
6.2
Audio Class D Amplifier (CLASSD)
6.3
Inter-IC Sound Multi-Channel Controller (I2SMCC)
6.3.1
Description
6.3.2
Embedded Characteristics
6.3.3
Block Diagram
6.3.4
I/O Lines Description
6.3.5
Product Dependencies
6.3.6
Functional Description
6.3.6.1
Initialization
6.3.6.2
Basic Operation
6.3.6.3
Host, Controller and Client Modes
6.3.6.4
I
2
S Reception and Transmission Sequence
6.3.6.5
Left-Justified Reception and Transmission Sequence
6.3.6.6
TDM Reception and Transmission Sequence
6.3.6.7
Serial Clock and Word Select Generation
6.3.6.8
Mono
6.3.6.9
Holding Registers
6.3.6.10
DMA
Controller Operation
6.3.6.11
Loop-back Mode
6.3.6.12
Interrupts
6.3.6.13
Register Write Protection
6.3.6.14
Functional Safety (Protection, Monitors and Reports)
6.3.7
Register Summary
6.4
Synchronous Serial Controller (SSC)
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
6.3.6 Functional Description
