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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
Product Pages
SAM9X60
  1. Home
  2. 8 Connectivity Subsystem
  3. 8.3 Flexible Serial Communication Controller (FLEXCOM)
  4. 8.3.7 USART Functional Description
  5. 8.3.7.9 LON Mode
  6. 8.3.7.9.2 Receiver and Transmitter Control

  • Introduction
  • Reference Document
  • 1 Overview
  • 2 CPU and Interconnect
  • 3 Memories
  • 4 System Controller
  • 5 Image Subsystem
  • 6 Audio Subsystem
  • 7 Security and Cryptography Subsystem
  • 8 Connectivity Subsystem
    • 8.1 Overview
    • 8.2 Ethernet MAC 10/100 (EMAC)
    • 8.3 Flexible Serial Communication Controller (FLEXCOM)
      • 8.3.1 Description
      • 8.3.2 Embedded Characteristics
      • 8.3.3 Block Diagram
      • 8.3.4 I/O Lines Description
      • 8.3.5 Product Dependencies
      • 8.3.6 Register Accesses
      • 8.3.7 USART Functional Description
        • 8.3.7.1 Baud Rate Generator
        • 8.3.7.2 Receiver and Transmitter Control
        • 8.3.7.3 Synchronous and Asynchronous Modes
        • 8.3.7.4 ISO7816 Mode
        • 8.3.7.5 IrDA Mode
        • 8.3.7.6 RS485 Mode
        • 8.3.7.7 USART Comparison Function on Received Character
        • 8.3.7.8 LIN Mode
        • 8.3.7.9 LON Mode
          • 8.3.7.9.1 Mode of Operation
          • 8.3.7.9.2 Receiver and Transmitter Control
          • 8.3.7.9.3 Character Transmission
          • 8.3.7.9.4 Character Reception
          • 8.3.7.9.5 LON Frame
          • 8.3.7.9.6 LON Operating Modes
          • 8.3.7.9.7 LON Node Backlog Estimation
          • 8.3.7.9.8 LON Timings
          • 8.3.7.9.9 LON Errors
          • 8.3.7.9.10 Drift Compensation
          • 8.3.7.9.11 LON Frame Handling
          • 8.3.7.9.12 LON Frame Handling with the Peripheral DMA Controller
        • 8.3.7.10 Test Modes
        • 8.3.7.11 USART FIFOs
        • 8.3.7.12 16-bit Data Protocol Support
        • 8.3.7.13 USART Register Write Protection
      • 8.3.8 SPI Functional Description
      • 8.3.9 TWI Functional Description
      • 8.3.10 Register Summary
    • 8.4 Quad Serial Peripheral Interface (QSPI)
    • 8.5 Secure Digital MultiMedia Card Controller (SDMMC)
    • 8.6 Controller Area Network (CAN)
    • 8.7 Timer Counter (TC)
    • 8.8 Pulse Width Modulation Controller (PWM)
  • 9 USB Subsystem
  • 10 Electrical and Mechanical Characteristics
  • 11 Revision History
  • Microchip Information

8.3.7.9.2 Receiver and Transmitter Control

See Receiver and Transmitter Control.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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