8.2.2 Embedded Characteristics

  • EMAC0 supports MII and RMII Interfaces to the Physical Layer (EMAC1 supports RMII only)
  • Compatible with IEEE Standard 802.3
  • 10 and 100 Mbit/s Operation
  • Full- and Half-duplex Operation
  • Statistics Counter Registers
  • Interrupt Generation to Signal Receive and Transmit Completion
  • DMA Host on Receive and Transmit Channels
  • Transmit and Receive FIFOs
  • Automatic Pad and CRC Generation on Transmitted Frames
  • Automatic Discard of Frames Received with Errors
  • Address Checking Logic Supports Up to Four Specific 48-bit Addresses
  • Supports Promiscuous Mode Where All Valid Received Frames are Copied to Memory
  • Hash Matching of Unicast and Multicast Destination Addresses
  • Physical Layer Management through MDIO Interface
  • Half-duplex Flow Control by Forcing Collisions on Incoming Frames
  • Full-duplex Flow Control with Recognition of Incoming Pause Frames
  • Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and Priority Tagged Frames
  • Multiple Buffers per Receive and Transmit Frame
  • Wake-on-LAN Support
  • Jumbo Frames Up to 10240 bytes Supported