33.3.2.4 Output Enable Timer Protection for GPIO Configuration

When the RESET Pin Configuration (RSTPINCFG) bits in FUSE.SYSCFG0 are 0x0, the RESET pin is configured as GPIO. To avoid a potential conflict between the GPIO actively driving the output and a 12V UPDI enable sequence initiation, the GPIO output driver is disabled for 768 OSC32K cycles after a System Reset. Enable any interrupts for this pin only after this period.

It is always recommended to issue a System Reset before entering the 12V programming sequence.