20.2.1 Block Diagram

The figure below shows a detailed block diagram of the timer/counter.

Figure 20-2. Timer/Counter Block Diagram

The counter register (TCAn.CNT), period registers with buffer (TCAn.PER and TCAn.PERBUF), and compare registers with buffers (TCAn.CMPx and TCAn.CMPBUFx) are 16-bit registers. All buffer registers have a buffer valid (BV) flag that indicates when the buffer contains a new value.

During normal operation, the counter value is continuously compared to zero and the period (PER) value to determine whether the counter has reached TOP or BOTTOM.

The counter value is also compared to the TCAn.CMPx registers. These comparisons can be used to generate interrupt requests. The Waveform Generator modes use these comparisons to set the waveform period or pulse-width.

A prescaled peripheral clock and events from the event system can be used to control the counter.

Figure 20-3. Timer/Counter Clock Logic