10.2.1 Block Diagram - CLKCTRL

Figure 10-1. CLKCTRL Block Diagram
The clock system consists of the main clock and other asynchronous clocks:
  • Main Clock

    This clock is used by the CPU, RAM, Flash, the I/O bus, and all peripherals connected to the I/O bus. It is always running in Active and Idle Sleep mode and can be running in Standby Sleep mode if requested.

    The main clock CLK_MAIN is prescaled and distributed by the clock controller:
    • CLK_CPU is used by the CPU, SRAM, and the NVMCTRL peripheral to access the nonvolatile memory
    • CLK_PER is used by all peripherals that are not listed under asynchronous clocks.
  • Clocks running asynchronously to the main clock domain:
    • CLK_RTC is used by the RTC/PIT. It will be requested when the RTC/PIT is enabled. The clock source for CLK_RTC should only be changed if the peripheral is disabled.
    • CLK_WDT is used by the WDT. It will be requested when the WDT is enabled.
    • CLK_BOD is used by the BOD. It will be requested when the BOD is enabled in Sampled mode.

The clock source for the for the main clock domain is configured by writing to the Clock Select bits (CLKSEL) in the Main Clock Control A register (CLKCTRL.MCLKCTRLA). The asynchronous clock sources are configured by registers in the respective peripheral.