20.5.2 Control B - Normal Mode
Name: | CTRLB |
Offset: | 0x01 |
Reset: | 0x00 |
Property: | - |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CMP2EN | CMP1EN | CMP0EN | ALUPD | WGMODE[2:0] | |||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 4, 5, 6 – CMPEN Compare n Enable
Value | Description |
---|---|
0 | Port output settings for the pin with WOn output respected |
1 | Port output settings for pin with WOn output overridden in FRQ or PWM Waveform Generation mode |
Bit 3 – ALUPD Auto-Lock Update
The Auto-Lock Update feature controls the Lock Update (LUPD) bit in the TCAn.CTRLE register. When ALUPD is written to ‘1’, LUPD will be set to ‘1’ until the Buffer Valid (CMPnBV) bits of all enabled compare channels are ‘1’. This condition will clear LUPD.
It will remain cleared until the next UPDATE condition, where the buffer values will be transferred to the CMPn registers and LUPD will be set to ‘1’ again. This makes sure that CMPnBUF register values are not transferred to the CMPn registers until all enabled compare buffers are written.
Value | Description |
---|---|
0 | LUPD in TCA.CTRLE not altered by system |
1 | LUPD in TCA.CTRLE set and cleared automatically |
Bits 2:0 – WGMODE[2:0] Waveform Generation Mode
These bits select the Waveform Generation mode and control the counting sequence of the counter, TOP value, UPDATE condition, interrupt condition, and type of waveform that is generated.
No waveform generation is performed in the Normal mode of operation. For all other modes, the result from the waveform generator will only be directed to the port pins if the corresponding CMPnEN bit has been set to enable this. The port pin direction must be set as output.
WGMODE[2:0] | Group Configuration | Mode of Operation | Top | Update | OVF |
---|---|---|---|---|---|
000 | NORMAL | Normal | PER | TOP | TOP |
001 | FRQ | Frequency | CMP0 | TOP | TOP |
010 | - | Reserved | - | - | - |
011 | SINGLESLOPE | Single-slope PWM | PER | BOTTOM | BOTTOM |
100 | - | Reserved | - | - | - |
101 | DSTOP | Dual-slope PWM | PER | BOTTOM | TOP |
110 | DSBOTH | Dual-slope PWM | PER | BOTTOM | TOP and BOTTOM |
111 | DSBOTTOM | Dual-slope PWM | PER | BOTTOM | BOTTOM |
Value | Name | Description |
---|---|---|
0x0 | NORMAL | Normal operation mode |
0x1 | FRQ | Frequency mode |
0x3 | SINGLESLOPE | Single-slope PWM mode |
0x5 | DSTOP | Dual-slope PWM mode |
0x6 | DSBOTH | Dual-slope PWM mode |
0x7 | DSBOTTOM | Dual-slope PWM mode |
Other | - | Reserved |