13.3.1 Initialization

An interrupt must be initialized in the following order:

  1. Configure the CPUINT if the default configuration is not adequate (optional):
    • Vector handling is configured by writing to the respective bits (IVSEL and CVT) in the Control A register (CPUINT.CTRLA).
    • Vector prioritizing by round robin is enabled by writing a '1' to the Round Robin Priority Enable bit (LVL0RR) in CPUINT.CTRLA.
    • Select the priority level 1 vector by writing its address to the Interrupt Vector (LVL1VEC) in the Level 1 Priority register (CPUINT.LVL1VEC).
  2. Configure the interrupt conditions within the peripheral, and enable the peripheral's interrupt.
  3. Enable interrupts globally by writing a '1' to the Global Interrupt Enable bit (I) in the CPU Status register (CPU.SREG).