3.1.3 Shutdown and Reset Circuitry

The processor controls the Auto-Maintain state and power-down by asserting the SHDN pin. At power-up, the SHDN signal is asserted at high level, sending the instruction to maintain power to the PMIC device. At power-down, SHDN is asserted at low level, PMIC shuts down all the supplies and enters Power-down mode.

The board includes three reset sources for the SAMA7G5 MPU:

• Power-on reset from the MCP16502 power management unit
• User push button reset (SW2)
• External JTAG or J-Link-OB reset from an in-circuit emulator

Some elements on the board (such as Ethernet PHYs, octal SPI memory and mikroBUS sockets) can be reset by the MPU independently from the general reset. They are connected by default to the NRST_OUT signal of the SAMA7G5 device and each of them can be controlled by the general reset line. A resistor swap must be performed for this configuration.

The figure below shows the shutdown connection and the reset circuitry.