24.5 Events

The RTC, when enabled, will generate the following output events:

  • Overflow (OVF): Generated when the counter has reached its top value and wrapped to zero. The generated strobe is synchronous with CLK_RTC and lasts one CLK_RTC cycle.
  • Compare (CMP): Indicates a match between the counter value and the Compare register. The generated strobe is synchronous with CLK_RTC and lasts one CLK_RTC cycle.

When enabled, the PIT generates the following 50% duty cycle clock signals on its event outputs:

  • Event 0: Clock period = 8192 RTC clock cycles
  • Event 1: Clock period = 4096 RTC clock cycles
  • Event 2: Clock period = 2048 RTC clock cycles
  • Event 3: Clock period = 1024 RTC clock cycles
  • Event 4: Clock period = 512 RTC clock cycles
  • Event 5: Clock period = 256 RTC clock cycles
  • Event 6: Clock period = 128 RTC clock cycles
  • Event 7: Clock period = 64 RTC clock cycles

The event users are configured by the Event System (EVSYS).