4.1 Revision History

Doc. Rev.	Date	Comments
C	09/2021	Added erratum: TCD: Halting TCD and Wait for SW Restart Does Not Work if Compare Value A is ‘`0`’ or Dual Slope Mode is Used Added data sheet clarifications: Memories: Fuses - Factory Default Values SLPCTRL: Sleep Mode Activity Overview USART: TXDATA Buffer Updated erratum: TWI : TIMEOUT Bits in the TWI.MCTRLA Register are Not Accessible Removed invalid erratum: Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode Editorial updates
B	11/2020	Added die revision B to document Added errata: CCL: The CCL Must be Disabled to Change the Configuration of a Single LUT TCA: Restart Will Reset Counter Direction in NORMAL and FRQ Mode TCB: CCMP and CNT Registers Operate as 16-Bit Registers in 8-Bit PWM Mode TCD: Asynchronous Input Events Not Working When TCD Counter Prescaler is Used USART: Start-of-Frame Detection Can Unintentionally be Enabled in Active Mode when RXCIF is ‘`0`’
A	05/2020	Initial document release The content of the document has been restructured from: ATtiny1614 Silicon Errata and Data Sheet Clarification ATtiny1616/3216 Silicon Errata and Data Sheet Clarification ATtiny1617/3217 Silicon Errata and Data Sheet Clarification to: ATtiny1614/1616/1617 Silicon Errata and Data Sheet Clarification (this document) ATtiny3216/3217 Silicon Errata and Data Sheet Clarification Refer to Appendix - Obsolete Revision History for further details. The following items are referring to changes between the latest revisions of the obsolete documents and this document: Added errata: Device: Writing the OSCLOCK Fuse in FUSE.OSCCFG to '1' Prevents Automatic Loading of Calibration Values USART: Open-Drain Mode Does Not Work When TXD is Configured as Output Removed data sheet clarifications, as the data sheet has been updated with correct information

C

09/2021

Added erratum:
- TCD: Halting TCD and Wait for SW Restart Does Not Work if Compare Value A is ‘0’ or Dual Slope Mode is Used

Added data sheet clarifications:
- Memories: Fuses - Factory Default Values
- SLPCTRL: Sleep Mode Activity Overview
- USART: TXDATA Buffer
Updated erratum:
- TWI : TIMEOUT Bits in the TWI.MCTRLA Register are Not Accessible
Removed invalid erratum:
- Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode
Editorial updates

B

11/2020

Added die revision B to document
Added errata:
- CCL: The CCL Must be Disabled to Change the Configuration of a Single LUT
- TCA: Restart Will Reset Counter Direction in NORMAL and FRQ Mode
- TCB: CCMP and CNT Registers Operate as 16-Bit Registers in 8-Bit PWM Mode
- TCD: Asynchronous Input Events Not Working When TCD Counter Prescaler is Used
- USART: Start-of-Frame Detection Can Unintentionally be Enabled in Active Mode when RXCIF is ‘0’

A

05/2020

Initial document release

The content of the document has been restructured from:

ATtiny1614 Silicon Errata and Data Sheet Clarification
ATtiny1616/3216 Silicon Errata and Data Sheet Clarification
ATtiny1617/3217 Silicon Errata and Data Sheet Clarification

to:

ATtiny1614/1616/1617 Silicon Errata and Data Sheet Clarification (this document)
ATtiny3216/3217 Silicon Errata and Data Sheet Clarification

Refer to Appendix - Obsolete Revision History for further details.

The following items are referring to changes between the latest revisions of the obsolete documents and this document:

Added errata:
- Device: Writing the OSCLOCK Fuse in FUSE.OSCCFG to '1' Prevents Automatic Loading of Calibration Values
- USART: Open-Drain Mode Does Not Work When TXD is Configured as Output
Removed data sheet clarifications, as the data sheet has been updated with correct information

ATtiny1614/1616/1617

4.1 Revision History