3 Pin Details of PIC32CX-BZ3 and WBZ35x Family

This section provides details on pin diagrams and signal names along with the device pinout for each variant of the SoC and module type of the PIC32CX-BZ3 and the WBZ35x family.

Figure 3-1. PIC32CX5109BZ31048 SoC Pinout Diagram

Figure 3-2. PIC32CX5109BZ31032 SoC Pinout Diagram

Note: It is required that the exposed paddle on the bottom of the SoC be connected to ground in the PCB.

Figure 3-3. WBZ351 and WBZ350 Module Pin Diagram (Top View)

Table 3-1. Pin Details of PIC32CX-BZ3 and WBZ35x Family
SoC		Module		Pin Name^(1)(2)(5)
PIC32CX5109BZ31032	PIC32CX5109BZ31048	WBZ351	WBZ350	Pin Name^(1)(2)(5)
0⁽³⁾	0⁽³⁾	0⁽³⁾, 1, 2, 8, 11, 19, 26	0⁽³⁾, 1, 5, 8, 18, 21, 27	GND
1	1	—	—	VPMU_VDD (PMU Core Circuit Power (1.9V-3.6V) Filtered version of main supply input)
—	2	22	—	QSPI_DATA0/RTC_IN3/RPA0/IOCA0/RA0
—	3	18	—	QSPI_SCK/RTC_IN2/RPA1/IOCA1/RA1
—	4	21	—	QSPI_DATA3/RTC_IN1/RPA2/IOCA2/RA2
2	5	24	19	SERCOM0_PAD0/RPA5/IOCA5/RA5
3	6	27, 28	16, 17	VDD (filtered version of main supply)
4	7	25	20	SERCOM0_PAD1/AC_CMP1_ALT/RPA6/IOCA6/RA6
5	8	31	25	SERCOM1_PAD0/RPA7/IOCA7/RA7
6	9	29	24	SERCOM1_PAD1/RPA8/IOCA8/RA8
7	10	30	22	SERCOM1_PAD2/RTC_IN0_ALT/RPA9/IOCA9/RA9
8	11	32	23	SERCOM1_PAD3/RTC_OUT_ALT/RPA10/IOCA10/RA10
—	12	23	—	QSPI_DATA1/RPB12/IOCB12/RB12
—	13	17	—	QSPI_CS/RTC_EVENT⁽⁶⁾/RPB13/IOCB13/RB13
9	14	15	14	CM4_SWDIO/SERCOM0_PAD2/RPB9/INT0/IOCB9/RB9
10	15	14	13	CM4_SWCLK/RPB8/IOCB8/RB8
11	16	16	3	SERCOM0_PAD3/RTC_OUT⁽⁶⁾/RPA4/IOCA4/RA4
—	17	33	—	SERCOM2_PAD0⁽⁷⁾/AC_CMP1/RPA13/IOCA13/RA13
—	18	34	—	SERCOM2_PAD1⁽⁷⁾/RPA14/IOCA14/RA14
12	19	3	2	NMCLR
13	20	—	—	VDDCORE (Secondary digital power supply) (1.2V ± 5%)
—	21	—	—	CLDO_IN (Secondary digital power supply) (1.2V ± 5%)
14	22	—	—	XO_N
15	23	—	—	XO_P
16	24	—	—	VDD_RF (RF block power supply, to be connected to RFLDO_OUT pin)
17	25	—	—	CLDO_OUT (Core LDO power supply 1.2V ± 5%)
18	26	—	—	RFLDO_OUT (RF LDO power supply (1.2V), to be connected to VDD_RF pin
19	27	—	—	BUCK_CLDO (RF/DIG CLDO supply)
20	28	—	—	BUCK_PA (RF MPA supply)
21	29	—	—	RF_IO
—	30	—	—	NC
—	31	4	—	AN4/CVD4/CVDR4/CVDT4/AC_AIN2/RPB0/IOCB0/RB0
—	32	38	—	AN5/CVD5/CVDR5/CVDT5/AC_AIN3/RPB1/IOCB1/RB1
—	33	37	—	AN6/CVD6/CVDR6/CVDT6/AC_AIN0/RPB2/IOCB2/RB2
—	34	5	—	AN7/CVD7/CVDR7/CVDT7/AC_AIN1/RPB3/IOCB3/RB3
22	35	39	11	AN0/CVD0/CVDR0/CVDT0/RPB4/IOCB4/RB4⁽⁸⁾
23	36	7	4	AVDD (VDDA)
24	37	6	9	AN1/CVD1/CVDR1/CVDT1/RPB5/IOCB5/RB5⁽⁸⁾
25	38	12	12	AN2/CVD2/CVDR2/CVDT2/RPB6/IOCB6/RB6⁽⁸⁾
26	39	13	15	CM4_SWO/AN3/CVD3/CVDR3/CVDT3/LVDIN/RPB7/IOCB7/RB7⁽⁸⁾
27	40	36	10	DACOUT/ANN0/RTC_IN0/RPA3/IOCA3/RA3
—	41	—	—	VDD
—	42	35	—	RPB10/IOCB10/RB10
—	43	20	—	QSPI_DATA2/RPB11/IOCB11/RB11
28	44	9	6	SOSCI/RA11⁽⁴⁾
29	45	10	7	SOSCO/RA12⁽⁴⁾
30	46	—	—	PMU_MLDO_BUCK_VSENSE/PMU_MLDO_OUT (PMU Output – MLDO_O)
31	47	—	—	VPMU_VDD
32	48	—	—	PMU_BK_LX
Note: The remappable peripherals can use all GPIOs (RAn and RBn) via PPS. All GPIOs (RAn and RBn) can be used as I/O Change Notification (IOCAn and IOCBn). Connect the metal paddle at the bottom of the device to the system ground. If not using the SOSC, use this pin as an input-only pin. The RTC_OUT and RTC_EVENT signals are multiplexed. Any one of the signal can be out at a time in pin-limited variants (32-pin variant). The SERCOM2 has only I²C functionality. The SERCOM2_PAD0 is I2C_SERCOM_SDA and the SERCOM2_PAD1 is I2C_SERCOM_SCL. The debug interface is the default functionality on these pins. The recommendation is to write ‘`0`’ to the CFGCON0.JTAGEN register during application initialization to use these pins for regular GPIO functionality.