26.13.1 Control A

Application software needs to check that the CTRLABUSY flag in the RTC.STATUS register is cleared before writing to this register.
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -

Bit 76543210 
 RUNSTDBYPRESCALER[3:0]CORREN RTCEN 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – RUNSTDBY Run in Standby

ValueDescription
0 RTC disabled in Standby sleep mode
1 RTC enabled in Standby sleep mode

Bits 6:3 – PRESCALER[3:0] Prescaler

These bits define the prescaling of the CLK_RTC clock signal. Due to synchronization between the RTC clock and the peripheral clock, there is a latency of two RTC clock cycles from updating the register until this has an effect.

ValueNameDescription
0x0 DIV1 RTC clock/1 (no prescaling)
0x1 DIV2 RTC clock/2
0x2 DIV4 RTC clock/4
0x3 DIV8 RTC clock/8
0x4 DIV16 RTC clock/16
0x5 DIV32 RTC clock/32
0x6 DIV64 RTC clock/64
0x7 DIV128 RTC clock/128
0x8 DIV256 RTC clock/256
0x9 DIV512 RTC clock/512
0xA DIV1024 RTC clock/1024
0xB DIV2048 RTC clock/2048
0xC DIV4096 RTC clock/4096
0xD DIV8192 RTC clock/8192
0xE DIV16384 RTC clock/16384
0xF DIV32768 RTC clock/32768

Bit 2 – CORREN Frequency Correction Enable

ValueDescription
0 Frequency correction is disabled
1 Frequency correction is enabled

Bit 0 – RTCEN RTC Peripheral Enable

ValueDescription
0 RTC peripheral is disabled
1 RTC peripheral is enabled