23.2.1 Internal Clock Source

When the Instruction clock (FOSC/4) is selected, the TMRx register will increment once every instruction cycle when the Timer1 prescaler is 1:1. If the Timer1 prescaler is set to a ratio other than 1:1, the timer will increment based on the number of instruction cycles related to the prescaler ratio. For example, if the Timer1 prescaler is 1:2, the timer will increment once every two instruction cycles.

When the FOSC clock source is selected, the TMRx register value will increment once every FOSC clock cycle, or four times per instruction cycle, when the Timer1 prescaler is 1:1. If the Timer1 prescaler is set to a ratio other than 1:1, the timer will increment based on the number of FOSC clock cycles related to the prescaler ratio. For example, if the Timer1 prescaler is 1:2, the timer will increment every other FOSC clock cycle, or twice every instruction cycle. Due to this condition, a two LSb error in resolution will occur when reading the TMRx value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input.

Important: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions:
  • Timer1 enabled after POR
  • Write to TMRxH or TMRxL
  • Timer1 is disabled
  • Timer1 is disabled (ON = 0) when TxCKI is high, then Timer1 is enabled (ON = 1) when TxCKI is low. Refer to the figure below.
Figure 23-2. Timer1 Incrementing Edge
Note:
  1. Arrows indicate counter increments.
  2. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.