8.2 Pin Description

The device features several PIO controllers that multiplex the I/O lines of the peripheral set. Table 8-1 defines how the I/O lines are multiplexed on the different PIO controllers. The "Reset State" column shows whether the PIO line resets in I/O mode or in Peripheral mode. If I/O is shown, the PIO line resets with the characteristics (input, output, pull-up or pull-down) indicated in this same column, so that the device is configured in a known state as soon as the reset is released. As a result, PIO_CFGR.FUNC resets to ‘0’. If a signal name is shown in the “Reset State” column, the PIO line is assigned to this function and PIO_CFGR.FUNC is not set to ‘0’. That is the case for pins controlling memories, in particular address lines, which require the pin to be driven as soon as the reset is released.

Table 8-1. Pin Description⁽¹⁾⁽²⁾
427-pin TFBGA	Power Rail	I/O Type ⁽³⁾	Primary		Alternate		PIO Peripheral				Reset State
427-pin TFBGA	Power Rail	I/O Type ⁽³⁾	Signal	Dir	Signal	Dir	Func	Signal	Dir	I/O Set	Signal, Dir, PU, PD, HiZ, ST⁽⁴⁾
W21	VDDSDMMC0	HSIO	PA0	I/O	–	–	A	SDMMC0_CK	O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO0	I/O	1
							C	NWE/NWR0/NANDWE	O	1
AA19	VDDSDMMC0	HSIO	PA1	I/O	–	–	A	SDMMC0_CMD	I/O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO1	I/O	1
							C	A21/NANDALE	O	1,2
W19	VDDSDMMC0	HSIO	PA2	I/O	–	–	A	SDMMC0_RSTN	O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO2	I/O	1
							C	A22/NANDCLE	O	1,2
Y19	VDDSDMMC0	HSIO	PA3	I/O	–	–	A	SDMMC0_DAT0	I/O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO3	I/O	1
							C	D0	I/O	1
W20	VDDSDMMC0	HSIO	PA4	I/O	–	–	A	SDMMC0_DAT1	I/O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO4	O	1
							C	D1	I/O	1
AA18	VDDSDMMC0	HSIO	PA5	I/O	–	–	A	SDMMC0_DAT4	I/O	1	PIO, I, PU, ST
							B	FLEXCOM2_IO0	I/O	3
							C	D4	I/O	1
							F	TCLK4	I	3
U19	VDDSDMMC0	HSIO	PA6	I/O	–	–	A	SDMMC0_DAT5	I/O	1	PIO, I, PU, ST
							B	FLEXCOM2_IO1	I/O	3
							C	D5	I/O	1
							F	TIOB4	I/O	3
AA17	VDDSDMMC0	HSIO	PA7	I/O	–	–	A	SDMMC0_DAT6	I/O	1	PIO, I, PU, ST
							B	FLEXCOM2_IO2	I/O	3
							C	D6	I/O	1
							F	TIOA4	I/O	3
T18	VDDSDMMC0	HSIO	PA8	I/O	–	–	A	SDMMC0_DAT7	I/O	1	PIO, I, PU, ST
							B	FLEXCOM2_IO3	I/O	3
							C	D7	I/O	1
							F	TIOA5	I/O	3
AA16	VDDSDMMC0	HSIO	PA9	I/O	–	–	A	SDMMC0_DAT2	I/O	1	PIO, I, PU, ST
							B	FLEXCOM0_IO2	I/O	1
							C	D2	I/O	1
							F	TIOB5	I/O	3
W17	VDDSDMMC0	HSIO	PA10	I/O	–	–	A	SDMMC0_DAT3	I/O	1	PIO, I, PU, ST
							B	FLEXCOM0_IO3	I/O	1
							C	D3	I/O	1
							F	TCLK5	I	3
V17	VDDSDMMC0	HSIO	PA11	I/O	–	–	A	SDMMC0_DS	I	1	PIO, I, PU, ST
							B	FLEXCOM0_IO4	O	1
							C	NANDRDY	I	1,2
							F	TIOB3	I/O	3
Y17	VDDSDMMC0	HSIO	PA12	I/O	–	–	B	FLEXCOM0_IO0	I/O	1	PIO, I, PU, ST
							C	NRD/NANDOE	O	1,2
							D	PCK0	O	1
							E	EXT_IRQ0	I	1
							F	TIOA3	I/O	3
U17	VDDSDMMC0	HSIO	PA13	I/O	–	–	B	FLEXCOM0_IO1	I/O	1	PIO, I, PU, ST
							C	NCS0/NANDCS0	O	1,2
							D	PCK1	O	1
							F	TCLK3	I	3
W13	VDDIOP0	GPIO	PA14	I/O	–	–	A	FLEXCOM4_IO4	O	1	PIO, I, PU, ST
							B	SDMMC0_WP	I	1
							C	FLEXCOM3_IO0	I/O	4
P15	VDDIOP0	GPIO	PA15	I/O	–	–	A	FLEXCOM4_IO3	I/O	1	PIO, I, PU, ST
							B	SDMMC0_1V8SEL	O	1
							C	FLEXCOM3_IO1	I/O	4
V11	VDDIOP0	GPIO	PA16	I/O	–	–	A	FLEXCOM4_IO2	I/O	1	PIO, I, PU, ST
							B	SDMMC0_CD	I	1
							D	PCK2	O	1
							E	EXT_IRQ1	I	1
R17	VDDIOP0	GPIO	PA17	I/O	–	–	A	FLEXCOM4_IO1	I/O	1	PIO, I, PU, ST
U11	VDDIOP0	GPIO	PA18	I/O	–	–	A	FLEXCOM4_IO0	I/O	1	PIO, I, PU, ST
V13	VDDIOP0	GPIO	PA19	I/O	–	–	A	TK0	I/O	1	PIO, I, PU, ST
							C	FLEXCOM4_IO5	O	1
							D	PWML0	O	3
T17	VDDIOP0	GPIO	PA20	I/O	–	–	A	TD0	O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO4	O	2
							C	FLEXCOM4_IO6	O	1
							D	PWMH0	O	3
U13	VDDIOP0	GPIO	PA21	I/O	–	–	A	TF0	I/O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO3	I/O	2
							D	PWML1	O	3
R15	VDDIOP0	GPIO	PA22	I/O	–	–	A	RD0	I	1	PIO, I, PU, ST
							B	FLEXCOM3_IO2	I/O	2
							C	PDMC0_DS1	I	1
							D	PWMH1	O	3
U15	VDDIOP0	GPIO	PA23	I/O	–	–	A	RK0	I/O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO1	I/O	2
							C	PDMC0_CLK	O	1
							D	PWML2	O	3
T13	VDDIOP0	GPIO	PA24	I/O	–	–	A	RF0	I/O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO0	I/O	2
							C	PDMC0_DS0	I	1
							D	PWMH2	O	3
R24	VDDGMAC0	GPIO	PA25	I/O	–	–	A	G0_TXCTL/G0_TXEN	O	1,2	PIO, I, PU, ST
R24	VDDGMAC0	GPIO	PA25	I/O	–	–	B	FLEXCOM6_IO2	I/O	1	PIO, I, PU, ST
R23	VDDGMAC0	GPIO	PA26	I/O	–	–	A	G0_TX0	O	1,2	PIO, I, PU, ST
R23	VDDGMAC0	GPIO	PA26	I/O	–	–	B	FLEXCOM6_IO3	I/O	1	PIO, I, PU, ST
N24	VDDGMAC0	GPIO	PA27	I/O	–	–	A	G0_TX1	O	1,2	PIO, I, PU, ST
N24	VDDGMAC0	GPIO	PA27	I/O	–	–	B	FLEXCOM6_IO4	O	1	PIO, I, PU, ST
L21	VDDGMAC0	GPIO	PA28	I/O	–	–	A	G0_RXCTL/G0_CRSDV	I	1,2	PIO, I, PU, ST
L21	VDDGMAC0	GPIO	PA28	I/O	–	–	B	FLEXCOM6_IO0	I/O	1	PIO, I, PU, ST
M25	VDDGMAC0	GPIO	PA29	I/O	–	–	A	G0_RX0	I	1,2	PIO, I, PU, ST
M25	VDDGMAC0	GPIO	PA29	I/O	–	–	B	FLEXCOM6_IO1	I/O	1	PIO, I, PU, ST
N23	VDDGMAC0	GPIO	PA30	I/O	–	–	A	G0_RX1	I	1,2	PIO, I, PU, ST
N23	VDDGMAC0	GPIO	PA30	I/O	–	–	B	FLEXCOM8_IO0	I/O	1	PIO, I, PU, ST
N25	VDDGMAC0	GPIO	PA31	I/O	–	–	A	G0_MDC	O	1,2	PIO, I, PU, ST
N25	VDDGMAC0	GPIO	PA31	I/O	–	–	B	FLEXCOM8_IO1	I/O	1	PIO, I, PU, ST
L20	VDDGMAC0	GPIO	PB0	I/O	–	–	A	G0_MDIO	I/O	1,2	PIO, I, PU, ST
L20	VDDGMAC0	GPIO	PB0	I/O	–	–	B	FLEXCOM8_IO3	I/O	1	PIO, I, PU, ST
P25	VDDGMAC0	GPIO	PB1	I/O	–	–	A	G0_REFCK/G0_TXCK	I/O	2,1	PIO, I, PU, ST
P25	VDDGMAC0	GPIO	PB1	I/O	–	–	B	FLEXCOM8_IO2	I/O	1	PIO, I, PU, ST
L23	VDDGMAC0	GPIO	PB2	I/O	–	–	A	G0_RX2	I	1	PIO, I, PU, ST
							B	FLEXCOM8_IO4	O	1
							C	G0_RXER	I	2
							D	RK0	I/O	2
R25	VDDGMAC0	GPIO	PB3	I/O	–	–	A	G0_RXCK	I	1	PIO, I, PU, ST
							B	FLEXCOM10_IO2	I/O	2
							D	TK0	I/O	2
L24	VDDGMAC0	GPIO	PB4	I/O	–	–	A	G0_TX2	O	1	PIO, I, PU, ST
							B	FLEXCOM10_IO3	I/O	2
							D	TF0	I/O	2
T25	VDDGMAC0	GPIO	PB5	I/O	–	–	A	G0_TX3	O	1	PIO, I, PU, ST
							B	FLEXCOM10_IO4	O	2
							D	TD0	O	2
L19	VDDGMAC0	GPIO	PB6	I/O	–	–	A	G0_RX3	I	1	PIO, I, PU, ST
							B	FLEXCOM10_IO0	I/O	2
							D	RD0	I	2
U25	VDDGMAC0	GPIO	PB7	I/O	–	–	A	G0_TSUCOMP	O	1,2	PIO, I, PU, ST
							B	FLEXCOM10_IO1	I/O	2
							C	ADTRG	I	1
							D	RF0	I/O	2
U23	VDDQSPI0	HSIO	PB8	I/O	–	–	A	QSPI0_IO3	I/O	1	PIO, I, PU, ST
							B	PCK3	O	1
							D	FLEXCOM2_IO1	I/O	2
V24	VDDQSPI0	HSIO	PB9	I/O	–	–	A	QSPI0_IO2	I/O	1	PIO, I, PU, ST
							D	FLEXCOM2_IO0	I/O	2
							E	PWMEXTRG0	I	1
N21	VDDQSPI0	HSIO	PB10	I/O	–	–	A	QSPI0_IO1	I/O	1	PIO, I, PU, ST
							D	FLEXCOM2_IO4	O	2
							E	PWMEXTRG1	I	1
U22	VDDQSPI0	HSIO	PB11	I/O	–	–	A	QSPI0_IO0	I/O	1	PIO, I, PU, ST
							D	FLEXCOM2_IO5	O	2
							E	PWML3	O	1
							F	TIOB3	I/O	2
R20	VDDQSPI0	HSIO	PB12	I/O	–	–	A	QSPI0_CS	O	1	PIO, I, PU, ST
							D	FLEXCOM2_IO3	I/O	2
							E	PWMFI1	I	1
							F	TIOA3	I/O	2
N20	VDDQSPI0	HSIO	PB13	I/O	–	–	A	QSPI0_SCK	O	1	PIO, I, PU, ST
							D	FLEXCOM2_IO2	I/O	2
							E	PWMFI0	I	1
							F	TCLK3	I	2
R21	VDDQSPI0	HSIO	PB14	I/O	–	–	A	QSPI0_SCKN	O	1	PIO, I, PU, ST
							B	QSPI1_SCK	O	1
							C	I2SMCC0_CK	I/O	3
							D	FLEXCOM10_IO5	O	1
							E	PWMH3	O	1
							G	FLEXCOM2_IO1	I/O	4
R22	VDDQSPI0	HSIO	PB15	I/O	–	–	A	QSPI0_IO4	I/O	1	PIO, I, PU, ST
							B	QSPI1_IO0	I/O	1
							C	I2SMCC0_WS	I/O	3
							D	FLEXCOM10_IO6	O	1
							E	PWML0	O	1
							F	TCLK4	I	2
							G	FLEXCOM2_IO0	I/O	4
U24	VDDQSPI0	HSIO	PB16	I/O	–	–	A	QSPI0_IO5	I/O	1	PIO, I, PU, ST
							B	QSPI1_IO1	I/O	1
							C	I2SMCC0_DIN0	I	3
							D	FLEXCOM10_IO4	O	1
							E	PWMH0	O	1
							F	TIOB4	I/O	2
M20	VDDQSPI0	HSIO	PB17	I/O	–	–	A	QSPI0_IO6	I/O	1	PIO, I, PU, ST
							B	QSPI1_IO2	I/O	1
							C	I2SMCC0_DOUT0	O	3
							D	FLEXCOM10_IO3	I/O	1
							E	PWML1	O	1
							F	TIOA4	I/O	2
V25	VDDQSPI0	HSIO	PB18	I/O	–	–	A	QSPI0_IO7	I/O	1	PIO, I, PU, ST
							B	QSPI1_IO3	I/O	1
							C	I2SMCC0_MCK	O	3
							D	FLEXCOM10_IO2	I/O	1
							E	PWMH1	O	1
							F	TIOA5	I/O	2
N22	VDDQSPI0	HSIO	PB19	I/O	–	–	A	QSPI0_DQS	I	1	PIO, I, PU, ST
							B	EXT_IRQ1	I	2
							C	PCK4	O	1
							D	FLEXCOM10_IO1	I/O	1
							E	PWML2	O	1
							F	TIOB5	I/O	2
M19	VDDQSPI0	HSIO	PB20	I/O	–	–	A	QSPI0_INT	I	1	PIO, I, PU, ST
							B	QSPI1_CS	O	1
							D	FLEXCOM10_IO0	I/O	1
							E	PWMH2	O	1
							F	TCLK5	I	2
F17	VDDSDMMC1	HSIO	PB21	I/O	–	–	A	SDMMC1_RSTN	O	1	PIO, I, PU, ST
							B	FLEXCOM6_IO4	O	2
							C	TIOB2	I/O	2
							D	ADTRG	I	2
							E	EXT_IRQ0	I	2
A18	VDDSDMMC1	HSIO	PB22	I/O	–	–	A	SDMMC1_CMD	I/O	1	PIO, I, PU, ST
							B	FLEXCOM6_IO3	I/O	2
							C	TCLK2	I	2
D17	VDDSDMMC1	HSIO	PB23	I/O	–	–	A	SDMMC1_CK	O	1	PIO, I, PU, ST
							B	FLEXCOM6_IO2	I/O	2
							C	TIOA2	I/O	2
A17	VDDSDMMC1	HSIO	PB24	I/O	–	–	A	SDMMC1_DAT0	I/O	1	PIO, I, PU, ST
A17	VDDSDMMC1	HSIO	PB24	I/O	–	–	B	FLEXCOM6_IO0	I/O	2	PIO, I, PU, ST
C17	VDDSDMMC1	HSIO	PB25	I/O	–	–	A	SDMMC1_DAT1	I/O	1	PIO, I, PU, ST
							B	FLEXCOM6_IO1	I/O	2
							C	TIOB2	I/O	1
B17	VDDSDMMC1	HSIO	PB26	I/O	–	–	A	SDMMC1_DAT2	I/O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO0	I/O	3
							C	TCLK2	I	1
E17	VDDSDMMC1	HSIO	PB27	I/O	–	–	A	SDMMC1_DAT3	I/O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO1	I/O	3
							C	TIOA2	I/O	1
A4	VDDIN33	GPIO	PB28	I/O	AD12	I	A	SDMMC1_WP	I	1	PIO, I, PU, ST
							C	FLEXCOM1_IO0	I/O	3
							E	D15	I/O	1,2
E11	VDDIN33	GPIO	PB29	I/O	AD13	I	A	SDMMC1_CD	I	1	PIO, I, PU, ST
							B	I2SMCC0_MCK	O	1
							C	FLEXCOM1_IO1	I/O	3
							E	D14	I/O	1,2
B5	VDDIN33	GPIO	PB30	I/O	AD14	I	A	SDMMC1_1V8SEL	O	1	PIO, I, PU, ST
							B	I2SMCC1_MCK	O	1
							C	FLEXCOM1_IO2	I/O	3
							D	TIOA1	I/O	1
							E	NCS1/NANDCS1	O	1,2
B12	VDDIN33	GPIO	PB31	I/O	HHSA_CC1	I/O	A	PCK7	O	2	PIO, I, PU, ST
							B	I2SMCC1_DIN1	I	1
							C	FLEXCOM1_IO3	I/O	3
							D	TCLK1	I	1
							E	NWE/NWR0/NANDWE	O	2
F15	VDDIN33	GPIO	PC0	I/O	HHSA_CC2	I/O	A	PCK6	O	2	PIO, I, PU, ST
							B	I2SMCC1_DIN2	I	1
							C	FLEXCOM9_IO4	O	2
							D	TIOB1	I/O	1
							E	NWR1/NBS1	O	1,2
B11	VDDIN33	GPIO	PC1	I/O	HHSB_CC1	I/O	A	PCK5	O	1	PIO, I, PU, ST
							C	FLEXCOM9_IO2	I/O	2
							E	SMCK	O	1,2
E15	VDDIN33	GPIO	PC2	I/O	HHSB_CC2	I/O	A	EXT_IRQ0	I	3	PIO, I, PU, ST
							C	FLEXCOM9_IO3	I/O	2
							E	A11	O	1,2
F11	VDDIN33	GPIO	PC3	I/O	AD0	I	A	SPDIF_RX	I	2	PIO, I, PU, ST
							C	FLEXCOM9_IO0	I/O	2
							D	FLEXCOM0_IO4	O	2
							E	A10	O	1,2
A3	VDDIN33	GPIO	PC4	I/O	AD1	I	A	SPDIF_TX	O	2	PIO, I, PU, ST
							C	FLEXCOM9_IO1	I/O	2
							D	FLEXCOM0_IO3	I/O	2
							E	D0	I/O	2
G13	VDDIN33	GPIO	PC5	I/O	AD2	I	A	I3CC_SDASPUE	O	1	PIO, I, PU, ST
							B	I2SMCC1_DIN3	I	1
							D	FLEXCOM0_IO2	I/O	2
							E	D1	I/O	2
J13	VDDIN33	GPIO	PC6	I/O	AD3	I	A	I3CC_SCL	I/O	1	PIO, I, PU, ST
							D	FLEXCOM0_IO1	I/O	2
							E	D4	I/O	2
C9	VDDIN33	GPIO	PC7	I/O	AD4	I/O	A	I3CC_SDA	I/O	1	PIO, I, PU, ST
							D	FLEXCOM0_IO0	I/O	2
							E	D5	I/O	2
D13	VDDIN33	GPIO	PC8	I/O	ACC_INP1	I	A	I2SMCC0_DIN1	I	1	PIO, I, PU, ST
							B	PDMC0_DS1	I	2
							C	I2SMCC1_DOUT1	O	1
							D	FLEXCOM9_IO0	I/O	1
							E	D6	I/O	2
B7	VDDIN33	GPIO	PC9	I/O	ACC_INN1	I	A	I2SMCC0_DIN2	I	1	PIO, I, PU, ST
							B	PDMC0_CLK	O	2
							C	I2SMCC1_DOUT2	O	1
							D	FLEXCOM9_IO1	I/O	1
							E	D7	I/O	2
H13	VDDIN33	GPIO	PC10	I/O	AD5	I/O	A	I2SMCC0_DIN3	I	1	PIO, I, PU, ST
							B	PDMC0_DS0	I	2
							C	I2SMCC1_DOUT3	O	1
							D	FLEXCOM9_IO2	I/O	1
							E	D2	I/O	2
C5	VDDIN33	GPIO	PC11	I/O	AD6	I	A	I2SMCC0_DOUT1	O	1	PIO, I, PU, ST
							B	PDMC1_DS0	I	1
							D	FLEXCOM9_IO3	I/O	1
							E	D3	I/O	2
H11	VDDIN33	GPIO	PC12	I/O	AD7	I	A	I2SMCC0_DOUT2	O	1	PIO, I, PU, ST
							B	PDMC1_CLK	O	1
							D	FLEXCOM9_IO4	O	1
							E	A9	O	1,2
C7	VDDIN33	GPIO	PC13	I/O	AD8	I	A	I2SMCC0_DOUT3	O	1	PIO, I, PD, ST
							B	PDMC1_DS1	I	1
							E	A8	O	1,2
J14	VDDIN33	GPIO	PC14	I/O	AD9	I	A	I2SMCC1_DIN0	I	1	PIO, I, PD, ST
							B	SPDIF_RX	I	3
							C	FLEXCOM1_IO0	I/O	2
							E	A7	O	1,2
D7	VDDIN33	GPIO	PC15	I/O	AD10	I	A	I2SMCC1_WS	I/O	1	PIO, I, PD, ST
							B	PDMC1_DS1	I	2
							C	FLEXCOM1_IO1	I/O	2
							E	A6	O	1,2
J11	VDDIN33	GPIO	PC16	I/O	AD11	I	A	I2SMCC1_CK	I/O	1	PIO, I, PD, ST
							B	PDMC1_CLK	O	2
							C	FLEXCOM1_IO2	I/O	2
							D	TIOA1	I/O	2
							E	A5	O	1,2
A8	VDDIN33	GPIO	PC17	I/O	ACC_INP0	I	A	I2SMCC1_DOUT0	O	1	PIO, I, PU, ST
							B	PDMC1_DS0	I	2
							C	FLEXCOM1_IO3	I/O	2
							D	TCLK1	I	2
							E	A4	O	1,2
E13	VDDIN33	GPIO	PC18	I/O	ACC_INN2	I	A	I2SMCC0_DIN0	I	1	PIO, I, PU, ST
							B	SPDIF_TX	O	3
							C	FLEXCOM1_IO4	O	2
							D	TIOB1	I/O	2
							E	A3	O	1,2
A7	VDDIN33	GPIO	PC19	I/O	ACC_INP2	I	A	I2SMCC0_WS	I/O	1	PIO, I, PU, ST
							B	PCK6	O	1
							E	A2	O	1,2
A6	VDDIN33	GPIO	PC20	I/O	ACC_INN3	–	A	I2SMCC0_DOUT0	O	1	PIO, I, PU, ST
A6	VDDIN33	GPIO	PC20	I/O	ACC_INN3	–	E	A1	O	1,2	PIO, I, PU, ST
G15	VDDIN33	GPIO	PC21	I/O	ACC_INP3	–	A	I2SMCC0_CK	I/O	1	PIO, I, PU, ST
							B	PCK7	O	1
							E	A0/NBS0	O	1,2
D9	VDDIN33	GPIO	PC22	I/O	AD15	–	A	NTRST	I	1	NTRST, PU, ST
D9	VDDIN33	GPIO	PC22	I/O	AD15	–	E	NWAIT	I	1,2	NTRST, PU, ST
A5	VDDIN33	GPIO	PC23	I/O	–	–	A	TCK_SWCLK	I	1	TCK_SWCLK, ST
D11	VDDIN33	GPIO	PC24	I/O	–	–	A	TMS_SWDIO	I/O	1	TMS_SWDIO, PU, ST
B6	VDDIN33	GPIO	PC25	I/O	–	–	A	TDI	I	1	TDI, PU, ST
F13	VDDIN33	GPIO	PC26	I/O	–	–	A	TDO	O	1	TDO, ST
F13	VDDIN33	GPIO	PC26	I/O	–	–	E	A12	O	1,2	TDO, ST
A19	VDDSDMMC2	HSIO	PC27	I/O	–	–	A	SDMMC2_CMD	I/O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO0	I/O	2
							D	TD1	O	2
							E	D8	I/O	1,2
B19	VDDSDMMC2	HSIO	PC28	I/O	–	–	A	SDMMC2_CK	O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO1	I/O	2
							D	TF1	I/O	2
							E	D9	I/O	1,2
A20	VDDSDMMC2	HSIO	PC29	I/O	–	–	A	SDMMC2_DAT0	I/O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO2	I/O	2
							D	TK1	I/O	2
							E	D10	I/O	1,2
							F	TCLK0	I	1
C19	VDDSDMMC2	HSIO	PC30	I/O	–	–	A	SDMMC2_DAT1	I/O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO3	I/O	2
							D	RD1	I	2
							E	D11	I/O	1,2
							F	TIOA0	I/O	1
B20	VDDSDMMC2	HSIO	PC31	I/O	–	–	A	SDMMC2_DAT2	I/O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO4	O	2
							C	PCK0	O	2
							D	RK1	I/O	2
							E	D12	I/O	1,2
							F	TIOB0	I/O	1
D20	VDDSDMMC2	HSIO	PD0	I/O	–	–	A	SDMMC2_DAT3	I/O	1	PIO, I, PU, ST
							C	PCK1	O	2
							D	RF1	I/O	2
							E	D13	I/O	1,2
A21	VDDIOP1	GPIO	PD1	I/O	–	–	A	SDMMC2_WP	I	1	PIO, I, PU, ST
							B	FLEXCOM1_IO5	O	1
							C	LCDC_HSYNC	O	2
							D	FLEXCOM3_IO0	I/O	3
D19	VDDIOP1	GPIO	PD2	I/O	–	–	A	SDMMC2_CD	I	1	PIO, I, PU, ST
							B	FLEXCOM1_IO6	O	1
							C	LCDC_VSYNC	O	2
							D	FLEXCOM3_IO1	I/O	3
B21	VDDIOP1	GPIO	PD3	I/O	–	–	A	SDMMC2_1V8SEL	O	1	PIO, I, PU, ST
							B	FLEXCOM1_IO4	O	1
							C	TIOA0	I/O	2
							D	FLEXCOM3_IO2	I/O	3
							E	EXT_IRQ1	I	3
G20	VDDIOP1	GPIO	PD4	I/O	–	–	A	LCDC_HSYNC	O	1	PIO, I, PU, ST
							B	FLEXCOM1_IO2	I/O	1
							C	TIOB0	I/O	2
							D	FLEXCOM7_IO1	I/O	3
C21	VDDIOP1	GPIO	PD5	I/O	–	–	A	LCDC_VSYNC	O	1	PIO, I, PU, ST
							B	FLEXCOM1_IO3	I/O	1
							C	TCLK0	I	2
							D	FLEXCOM7_IO0	I/O	3
E21	VDDIOP1	GPIO	PD6	I/O	–	–	A	LCDC_PWM	O	1,2	PIO, I, PU, ST
							B	FLEXCOM1_IO1	I/O	1
							D	FLEXCOM7_IO2	I/O	3
B22	VDDIOP1	GPIO	PD7	I/O	–	–	A	LCDC_DISP	O	1,2	PIO, I, PU, ST
							B	FLEXCOM1_IO0	I/O	1
							D	FLEXCOM7_IO3	I/O	3
G21	VDDIOP1	GPIO	PD8	I/O	–	–	A	CANTX0	O	1	PIO, I, PU, ST
G21	VDDIOP1	GPIO	PD8	I/O	–	–	B	FLEXCOM7_IO0	I/O	1	PIO, I, PU, ST
A22	VDDIOP1	GPIO	PD9	I/O	–	–	A	CANRX0	I	1	PIO, I, PU, ST
A22	VDDIOP1	GPIO	PD9	I/O	–	–	B	FLEXCOM7_IO1	I/O	1	PIO, I, PU, ST
E22	VDDIOP1	GPIO	PD10	I/O	–	–	A	CANTX1	O	1	PIO, I, PU, ST
							B	FLEXCOM7_IO2	I/O	1
							C	TIOA1	I/O	3
A23	VDDIOP1	GPIO	PD11	I/O	–	–	A	CANRX1	I	1	PIO, I, PU, ST
							B	FLEXCOM7_IO3	I/O	1
							C	TCLK1	I	3
B25	VDDIOP1	GPIO	PD12	I/O	–	–	A	CANTX2	O	1	PIO, I, PU, ST
							B	FLEXCOM7_IO4	O	1
							C	TIOB1	I/O	3
							D	PCK2	O	2
							E	FLEXCOM3_IO3	I/O	3
C23	VDDIOP1	GPIO	PD13	I/O	–	–	A	CANRX2	I	1	PIO, I, PU, ST
							B	FLEXCOM5_IO4	O	1
							C	TIOA2	I/O	3
							D	PCK3	O	2
C25	VDDIOP1	GPIO	PD14	I/O	–	–	A	CANTX3	O	1	PIO, I, PU, ST
							B	FLEXCOM5_IO2	I/O	1
							C	TIOB2	I/O	3
C24	VDDIOP1	GPIO	PD15	I/O	–	–	A	CANRX3	I	1	PIO, I, PU, ST
							B	FLEXCOM5_IO3	I/O	1
							C	TCLK2	I	3
D25	VDDIOP1	GPIO	PD16	I/O	–	–	A	CANTX4	O	1	PIO, I, PU, ST
D25	VDDIOP1	GPIO	PD16	I/O	–	–	B	FLEXCOM5_IO0	I/O	1	PIO, I, PU, ST
E23	VDDIOP1	GPIO	PD17	I/O	–	–	A	CANRX4	I	1	PIO, I, PU, ST
E23	VDDIOP1	GPIO	PD17	I/O	–	–	B	FLEXCOM5_IO1	I/O	1	PIO, I, PU, ST
G22	VDDGMAC1	GPIO	PD18	I/O	–	–	B	FLEXCOM6_IO0	I/O	4	PIO, I, PU, ST
							C	CANTX1	O	2
							D	PCK4	O	2
E24	VDDGMAC1	GPIO	PD19	I/O	–	–	B	FLEXCOM6_IO1	I/O	4	PIO, I, PU, ST
							C	CANRX1	I	2
							D	PCK2	O	3
J18	VDDGMAC1	GPIO	PD20	I/O	–	–	B	FLEXCOM6_IO2	I/O	4	PIO, I, PU, ST
							C	I2SMCC1_MCK	O	2
							D	PCK3	O	3
K19	VDDGMAC1	GPIO	PD21	I/O	–	–	A	G1_TXCTL/G1_TXEN	O	1,2	PIO, I, PU, ST
							B	FLEXCOM6_IO2	I/O	3
							C	TK1	I/O	1
E25	VDDGMAC1	GPIO	PD22	I/O	–	–	A	G1_TX0	O	1,2	PIO, I, PU, ST
							B	FLEXCOM6_IO3	I/O	3,4
							C	TF1	I/O	1
G23	VDDGMAC1	GPIO	PD23	I/O	–	–	A	G1_TX1	O	1,2	PIO, I, PU, ST
							B	FLEXCOM6_IO4	O	3,4
							C	TD1	O	1
F25	VDDGMAC1	GPIO	PD24	I/O	–	–	A	G1_RXCTL/G1_CRSDV	I	1,2	PIO, I, PU, ST
							B	FLEXCOM6_IO0	I/O	3
							C	RD1	I	1
							E	PDMC0_DS1	I	3
J20	VDDGMAC1	GPIO	PD25	I/O	–	–	A	G1_MDC	O	1,2	PIO, I, PU, ST
							B	FLEXCOM6_IO1	I/O	3
							C	RK1	I/O	1
							E	PDMC0_CLK	O	3
G25	VDDGMAC1	GPIO	PD26	I/O	–	–	A	G1_MDIO	I/O	1,2	PIO, I, PU, ST
							B	FLEXCOM7_IO4	O	2
							C	RF1	I/O	1
							D	I2SMCC1_DIN2	I	2
							E	PDMC0_DS0	I	3
J21	VDDGMAC1	GPIO	PD27	I/O	–	–	A	G1_RX0	I	1,2	PIO, I, PU, ST
							B	FLEXCOM7_IO0	I/O	2
							C	SPDIF_RX	I	1
							D	I2SMCC1_DIN3	I	2
G24	VDDGMAC1	GPIO	PD28	I/O	–	–	A	G1_RX1	I	1,2	PIO, I, PU, ST
							B	FLEXCOM7_IO1	I/O	2
							C	SPDIF_TX	O	1
							D	I2SMCC1_DIN1	I	2
J24	VDDGMAC1	GPIO	PD29	I/O	–	–	A	G1_REFCK/G1_TXCK	I/O	2,1	PIO, I, PU, ST
							B	FLEXCOM7_IO2	I/O	2
							C	I2SMCC1_DOUT3	O	2
H25	VDDGMAC1	GPIO	PD30	I/O	–	–	A	G1_RX2	I	1	PIO, I, PU, ST
							B	FLEXCOM7_IO3	I/O	2
							C	I2SMCC1_DOUT1	O	2
							D	PDMC1_DS1	I	3
							E	G1_RXER	I	2
J25	VDDGMAC1	GPIO	PD31	I/O	–	–	A	G1_RX3	I	1	PIO, I, PU, ST
							B	FLEXCOM5_IO4	O	2
							C	I2SMCC1_DOUT2	O	2
							D	PDMC1_DS0	I	3
J23	VDDGMAC1	GPIO	PE0	I/O	–	–	A	G1_TX2	O	1	PIO, I, PU, ST
							B	FLEXCOM5_IO2	I/O	2
							C	I2SMCC1_DIN0	I	2
							D	PDMC1_CLK	O	3
K25	VDDGMAC1	GPIO	PE1	I/O	–	–	A	G1_TX3	O	1	PIO, I, PU, ST
							B	FLEXCOM5_IO3	I/O	2
							C	I2SMCC1_WS	I/O	2
							D	PDMC0_DS1	I	4
J22	VDDGMAC1	GPIO	PE2	I/O	–	–	A	G1_RXCK	I	1	PIO, I, PU, ST
							B	FLEXCOM5_IO1	I/O	2
							C	I2SMCC1_CK	I/O	2
							D	PDMC0_CLK	O	4
L25	VDDGMAC1	GPIO	PE3	I/O	–	–	A	G1_TSUCOMP	O	1,2	PIO, I, PU, ST
							B	FLEXCOM5_IO0	I/O	2
							C	I2SMCC1_DOUT0	O	2
							D	PDMC0_DS0	I	4
Y11	VDDLVDS	GPIO	PE4	I/O	LVDS_A0M	O	A	LCDC_DAT0	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO2	I/O	1
							C	PWML0	O	2
							D	TIOA3	I/O	1
							E	I2SMCC0_DIN1	I	2
AA11	VDDLVDS	GPIO	PE5	I/O	LVDS_A0P	O	A	LCDC_DAT1	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO3	I/O	1
							C	PWMH0	O	2
							D	TIOB3	I/O	1
							E	I2SMCC0_DIN2	I	2
Y12	VDDLVDS	GPIO	PE6	I/O	LVDS_A1M	O	A	LCDC_DAT2	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO4	O	1
							C	PWML1	O	2
							D	TCLK3	I	1
							E	I2SMCC0_DIN3	I	2
AA12	VDDLVDS	GPIO	PE7	I/O	LVDS_A1P	O	A	LCDC_DAT3	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO5	O	1
							C	PWMH1	O	2
							D	TIOA4	I/O	1
							E	I2SMCC0_DOUT1	O	2
Y13	VDDLVDS	GPIO	PE8	I/O	LVDS_A2M	O	A	LCDC_DAT4	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO0	I/O	1
							C	PWML2	O	2
							D	TIOB4	I/O	1
							E	I2SMCC0_CK	I/O	2
AA13	VDDLVDS	GPIO	PE9	I/O	LVDS_A2P	O	A	LCDC_DAT5	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO1	I/O	1
							C	PWMH2	O	2
							D	TCLK4	I	1
							E	I2SMCC0_WS	I/O	2
Y15	VDDLVDS	GPIO	PE10	I/O	LVDS_A3M	O	A	LCDC_DAT6	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO6	O	1
							C	PWML3	O	2
							D	TIOA5	I/O	1
							E	I2SMCC0_DOUT2	O	2
AA15	VDDLVDS	GPIO	PE11	I/O	LVDS_A3P	O	A	LCDC_DAT7	O	1,2	PIO, I, PU, ST
							C	PWMH3	O	2
							D	TIOB5	I/O	1
							E	I2SMCC0_DOUT3	O	2
Y14	VDDLVDS	GPIO	PE12	I/O	LVDS_CLK1M	O	A	LCDC_DEN	O	1,2	PIO, I, PU, ST
							B	PCK3	O	4
							C	PWMEXTRG0	I	2
							D	TCLK5	I	1
							E	I2SMCC0_DIN0	I	2
AA14	VDDLVDS	GPIO	PE13	I/O	LVDS_CLK1P	O	A	LCDC_PCK	O	1,2	PIO, I, PU, ST
							B	PCK4	O	3
							C	PWMEXTRG1	I	2
							E	I2SMCC0_DOUT0	O	2
B4	VDDIN33	Analog input	ADVREFP	I	–	–	–	–	–	–	–
F14	VDDIN33	power	VDDIN33	I	–	–	–	–	–	–	–
H16	GNDIN33	ground	GNDIN33	I	–	–	–	–	–	–	–
F16	GNDANA	ground	GNDANA	I	–	–	–	–	–	–	–
E10	GNDANA	ground	GNDANA	I	–	–	–	–	–	–	–
E12	GNDANA	ground	GNDANA	I	–	–	–	–	–	–	–
N16	GNDANA	ground	GNDANA	I	–	–	–	–	–	–	–
Y18	VDDIOP0	power	VDDIOP0	I	–	–	–	–	–	–	–
K24	VDDGMAC0	power	VDDGMAC0	I	–	–	–	–	–	–	–
F21	VDDIOP1	power	VDDIOP1	I	–	–	–	–	–	–	–
F24	VDDGMAC1	power	VDDGMAC1	I	–	–	–	–	–	–	–
A1	GND	ground	GND	I	–	–	–	–	–	–	–
A25	GND	ground	GND	I	–	–	–	–	–	–	–
AA1	GND	ground	GND	I	–	–	–	–	–	–	–
AA4	GND	ground	GND	I	–	–	–	–	–	–	–
AA6	GND	ground	GND	I	–	–	–	–	–	–	–
D4	GND	ground	GND	I	–	–	–	–	–	–	–
D24	GND	ground	GND	I	–	–	–	–	–	–	–
E2	GND	ground	GND	I	–	–	–	–	–	–	–
E5	GND	ground	GND	I	–	–	–	–	–	–	–
E8	GND	ground	GND	I	–	–	–	–	–	–	–
E14	GND	ground	GND	I	–	–	–	–	–	–	–
E18	GND	ground	GND	I	–	–	–	–	–	–	–
E16	VDDANA	power	VDDANA	I	–	–	–	–	–	–	–
F10	VDDANA	power	VDDANA	I	–	–	–	–	–	–	–
F12	VDDANA	power	VDDOUT25	O	–	–	–	–	–	–	–
V15	VDDANA	power	VDDIN25	I	–	–	–	–	–	–	–
L1	GND	ground	GND		–	–	–	–	–	–	–
G11	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
N19	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
H12	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
F1	GND	ground	GND	I	–	–	–	–	–	–	–
K17	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
K20	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
L13	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
M12	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
N17	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
V19	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
P21	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
T14	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
T24	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
Y16	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
G19	VDDCPU	power	VDDCPU	I	–	–	–	–	–	–	–
H20	VDDCPU	power	VDDCPU	I	–	–	–	–	–	–	–
H24	VDDCPU	power	VDDCPU	I	–	–	–	–	–	–	–
J19	VDDCPU	power	VDDCPU	I	–	–	–	–	–	–	–
K18	VDDCPU	power	VDDCPU	I	–	–	–	–	–	–	–
J17	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
F9	GND	ground	GND	I	–	–	–	–	–	–	–
F20	GND	ground	GND	I	–	–	–	–	–	–	–
G2	GND	ground	GND	I	–	–	–	–	–	–	–
G3	GND	ground	GND	I	–	–	–	–	–	–	–
G5	GND	ground	GND	I	–	–	–	–	–	–	–
G7	GND	ground	GND	I	–	–	–	–	–	–	–
G9	GND	ground	GND	I	–	–	–	–	–	–	–
H1	GND	ground	GND	I	–	–	–	–	–	–	–
H5	GND	ground	GND	I	–	–	–	–	–	–	–
H8	GND	ground	GND	I	–	–	–	–	–	–	–
H10	GND	ground	GND	I	–	–	–	–	–	–	–
H18	GND	ground	GND	I	–	–	–	–	–	–	–
H21	GND	ground	GND	I	–	–	–	–	–	–	–
J1	GND	ground	GND	I	–	–	–	–	–	–	–
J3	GND	ground	GND	I	–	–	–	–	–	–	–
J5	GND	ground	GND	I	–	–	–	–	–	–	–
J7	GND	ground	GND	I	–	–	–	–	–	–	–
P16	GND	ground	GND	I	–	–	–	–	–	–	–
T16	VDDLVDS	power	VDDLVDS	I	–	–	–	–	–	–	–
H14	GNDUTMI	ground	GNDUTMI	I	–	–	–	–	–	–	–
J15	VDDUTMI	power	VDDUTMI	I	–	–	–	–	–	–	–
B1	VDDUTMI	–	HHSDPA	I/O	–	–	–	–	–	–	–
B2	VDDUTMI	–	HHSDMA	I/O	–	–	–	–	–	–	–
C1	VDDUTMI	–	HHSDPB	I/O	–	–	–	–	–	–	–
C2	VDDUTMI	–	HHSDMB	I/O	–	–	–	–	–	–	–
D1	VDDUTMI	–	HHSDPC	I/O	–	–	–	–	–	–	–
D2	VDDUTMI	–	HHSDMC	I/O	–	–	–	–	–	–	–
C3	VDDUTMI	Analog input	HHSRTUNE	I	–	–	–	–	–	–	–
K12	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
K14	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
L9	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
L10	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
L11	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
L15	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
M9	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
M10	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
M14	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
M16	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
N11	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
N13	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
N15	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
P10	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
P12	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
J9	GND	ground	GND	I	–	–	–	–	–	–	–
J10	GND	ground	GND	I	–	–	–	–	–	–	–
K2	GND	ground	GND	I	–	–	–	–	–	–	–
K8	GND	ground	GND	I	–	–	–	–	–	–	–
K10	GND	ground	GND	I	–	–	–	–	–	–	–
K11	GND	ground	GND	I	–	–	–	–	–	–	–
K13	GND	ground	GND	I	–	–	–	–	–	–	–
K15	GND	ground	GND	I	–	–	–	–	–	–	–
K21	GND	ground	GND	I	–	–	–	–	–	–	–
AA8	GND	ground	GND	I	–	–	–	–	–	–	–
AA10	GND	ground	GND	I	–	–	–	–	–	–	–
AA25	GND	ground	GND	I	–	–	–	–	–	–	–
B16	GND	ground	GND	I	–	–	–	–	–	–	–
B24	GND	ground	GND	I	–	–	–	–	–	–	–
E4	VDDIODDR	Analog input	DDR_VREF	I	–	–	–	–	–	–	–
J12	VDDIODDR	Analog input	DDR_ZQ	O	–	–	–	–	–	–	–
P20	VDDDPHY	power	VDDDPHY	I	–	–	–	–	–	–	–
M21	GNDDPHY	ground	GNDDPHY	I	–	–	–	–	–	–	–
Y22	VDDDPHY	–	MIPI_CLKN	O	–	–	–	–	–	–	–
AA22	VDDDPHY	–	MIPI_CLKP	O	–	–	–	–	–	–	–
Y20	VDDDPHY	–	MIPI_DN0	O	–	–	–	–	–	–	–
AA20	VDDDPHY	–	MIPI_DP0	O	–	–	–	–	–	–	–
Y21	VDDDPHY	–	MIPI_DN1	O	–	–	–	–	–	–	–
AA21	VDDDPHY	–	MIPI_DP1	O	–	–	–	–	–	–	–
Y24	VDDDPHY	–	MIPI_DN2	O	–	–	–	–	–	–	–
Y25	VDDDPHY	–	MIPI_DP2	O	–	–	–	–	–	–	–
W24	VDDDPHY	–	MIPI_DN3	O	–	–	–	–	–	–	–
W25	VDDDPHY	–	MIPI_DP3	O	–	–	–	–	–	–	–
AA23	VDDDPHY	–	MIPI_REXT	I	–	–	–	–	–	–	–
U21	VDDSDMMC0	power	VDDSDMMC0	I	–	–	–	–	–	–	–
B18	VDDSDMMC1	power	VDDSDMMC1	I	–	–	–	–	–	–	–
T20	VDDSDMMC0	Analog input	SDMMC0_CAL	I	–	–	–	–	–	–	–
F18	VDDSDMMC1	Analog input	SDMMC1_CAL	I	–	–	–	–	–	–	–
D22	VDDSDMMC2	power	VDDSDMMC2	I	–	–	–	–	–	–	–
E19	VDDSDMMC2	Analog input	SDMMC2_CAL	I	–	–	–	–	–	–	–
J16	GNDBAT	ground	GNDBAT	I	–	–	–	–	–	–	–
K16	VBAT	power	VBAT	I	–	–	–	–	–	–	–
G17	VBAT	PIOBU	PIOBU0	I	–	–	–	–	–	–	PU⁽⁵⁾
B14	VBAT	PIOBU	PIOBU1	I	–	–	–	–	–	–	PU⁽⁵⁾
C15	VBAT	PIOBU	PIOBU2	I	–	–	–	–	–	–	PU⁽⁵⁾
A13	VBAT	PIOBU	PIOBU3	I	–	–	–	–	–	–	PD⁽⁵⁾
B10	VDDIN33	–	XIN	I	–	–	–	–	–	–	–
A10	VDDIN33	–	XOUT	O	–	–	–	–	–	–	–
A15	VBAT	–	XIN32	I	–	–	–	–	–	–	–
B15	VBAT	–	XOUT32	O	–	–	–	–	–	–	–
D15	VBAT	–	TST	I	–	–	–	–	–	–	PD
C13	VBAT	–	JTAGSEL	I	–	–	–	–	–	–	PD
A16	VBAT	–	WKUP0	I	–	–	–	–	–	–	–
B13	VBAT	–	SHDN	O	–	–	–	–	–	–	–
B9	VDDIN33	–	NRST	I	–	–	–	–	–	–	PU
B8	VDDIN33	–	NRST_OUT	O	–	–	–	–	–	–	OD⁽⁶⁾
C11	VDDIN33	GPIO	AUDIOCLK	O	–	–	–	–	–	–	–
A12	VBAT	backup I/O	LPM	O	–	–	–	–	–	–	–
M24	VDDQSPI0	power	VDDQSPI0	I	–	–	–	–	–	–	–
L22	VDDQSPI0	Analog input	QSPI0_CAL	I	–	–	–	–	–	–	–
A14	GND	ground	GND	I	–	–	–	–	–	–	–
H15	GND	ground	GND	I	–	–	–	–	–	–	–
A11	GND	ground	GND	I	–	–	–	–	–	–	–
A9	GND	ground	GND	I	–	–	–	–	–	–	–
AA3	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
AA5	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
AA7	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
AA9	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
E1	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
E3	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
E7	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
E9	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
F2	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
F5	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
F6	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
F8	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
G1	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
G4	DDRM_ZQ	Analog input	DDRM_ZQ	I	–	–	–	–	–	–	–
G6	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
H2	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
H6	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
J2	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
J4	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
J6	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
K1	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
K5	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
K6	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
K7	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
K9	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
L2	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
L3	GND	ground	GND	I	–	–	–	–	–	–	–
L4	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
L5	GND	ground	GND	I	–	–	–	–	–	–	–
L6	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
L7	GND	ground	GND	I	–	–	–	–	–	–	–
L8	GND	ground	GND	I	–	–	–	–	–	–	–
L12	GND	ground	GND	I	–	–	–	–	–	–	–
L14	GND	ground	GND	I	–	–	–	–	–	–	–
L16	GND	ground	GND	I	–	–	–	–	–	–	–
L17	GND	ground	GND	I	–	–	–	–	–	–	–
L18	GND	ground	GND	I	–	–	–	–	–	–	–
M1	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
M2	GND	ground	GND	I	–	–	–	–	–	–	–
M5	GND	ground	GND	I	–	–	–	–	–	–	–
M6	GND	ground	GND	I	–	–	–	–	–	–	–
M7	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
M8	GND	ground	GND	I	–	–	–	–	–	–	–
M11	GND	ground	GND	I	–	–	–	–	–	–	–
M13	GND	ground	GND	I	–	–	–	–	–	–	–
M15	GND	ground	GND	I	–	–	–	–	–	–	–
M17	GND	ground	GND	I	–	–	–	–	–	–	–
M18	GND	ground	GND	I	–	–	–	–	–	–	–
N1	GND	ground	GND	I	–	–	–	–	–	–	–
N2	GND	ground	GND	I	–	–	–	–	–	–	–
N3	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
N4	GND	ground	GND	I	–	–	–	–	–	–	–
N5	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
N6	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
N7	GND	ground	GND	I	–	–	–	–	–	–	–
N8	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
N9	GND	ground	GND	I	–	–	–	–	–	–	–
N10	GND	ground	GND	I	–	–	–	–	–	–	–
N12	GND	ground	GND	I	–	–	–	–	–	–	–
N14	GND	ground	GND	I	–	–	–	–	–	–	–
N18	GND	ground	GND	I	–	–	–	–	–	–	–
P1	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
P2	GND	ground	GND	I	–	–	–	–	–	–	–
P5	GND	ground	GND	I	–	–	–	–	–	–	–
P6	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
P8	GND	ground	GND	I	–	–	–	–	–	–	–
P11	GND	ground	GND	I	–	–	–	–	–	–	–
P13	GND	ground	GND	I	–	–	–	–	–	–	–
P14	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
P18	GND	ground	GND	I	–	–	–	–	–	–	–
P24	GND	ground	GND	I	–	–	–	–	–	–	–
R1	GND	ground	GND	I	–	–	–	–	–	–	–
R2	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
R3	GND	ground	GND	I	–	–	–	–	–	–	–
R4	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
R5	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
R6	GND	ground	GND	I	–	–	–	–	–	–	–
R7	GND	ground	GND	I	–	–	–	–	–	–	–
R9	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
R10	GND	ground	GND	I	–	–	–	–	–	–	–
R11	GND	ground	GND	I	–	–	–	–	–	–	–
R12	DDR_VREF	Analog input	DDR_VREF	I	–	–	–	–	–	–	–
R13	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
R19	GND	ground	GND	I	–	–	–	–	–	–	–
T1	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
T2	GND	ground	GND	I	–	–	–	–	–	–	–
T5	GND	ground	GND	I	–	–	–	–	–	–	–
T6	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
T8	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
T9	GND	ground	GND	I	–	–	–	–	–	–	–
T10	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
T11	GND	ground	GND	I	–	–	–	–	–	–	–
T12	GND	ground	GND	I	–	–	–	–	–	–	–
T15	GND	ground	GND	I	–	–	–	–	–	–	–
T21	GND	ground	GND	I	–	–	–	–	–	–	–
U1	GND	ground	GND	I	–	–	–	–	–	–	–
U2	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
U3	GND	ground	GND	I	–	–	–	–	–	–	–
U4	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
U5	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
U7	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
U8	GND	ground	GND	I	–	–	–	–	–	–	–
U9	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
U10	GND	ground	GND	I	–	–	–	–	–	–	–
U12	GND	ground	GND	I	–	–	–	–	–	–	–
U14	GND	ground	GND	I	–	–	–	–	–	–	–
U16	GND	ground	GND	I	–	–	–	–	–	–	–
U18	GND	ground	GND	I	–	–	–	–	–	–	–
V1	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
V2	GND	ground	GND	I	–	–	–	–	–	–	–
V4	GND	ground	GND	I	–	–	–	–	–	–	–
V6	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
V7	GND	ground	GND	I	–	–	–	–	–	–	–
V9	GND	ground	GND	I	–	–	–	–	–	–	–
V20	GND	ground	GND	I	–	–	–	–	–	–	–
V22	GND	ground	GND	I	–	–	–	–	–	–	–
W1	GND	ground	GND	I	–	–	–	–	–	–	–
W2	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
W3	GND	ground	GND	I	–	–	–	–	–	–	–
W5	GND	ground	GND	I	–	–	–	–	–	–	–
W6	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
W7	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
W9	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
W11	GND	ground	GND	I	–	–	–	–	–	–	–
W15	GND	ground	GND	I	–	–	–	–	–	–	–
W23	GND	ground	GND	I	–	–	–	–	–	–	–
Y1	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
Y2	GND	ground	GND	I	–	–	–	–	–	–	–
Y4	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
Y5	GND	ground	GND	I	–	–	–	–	–	–	–
Y6	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
Y7	GND	ground	GND	I	–	–	–	–	–	–	–
Y8	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
Y9	GND	ground	GND	I	–	–	–	–	–	–	–
Y10	DDRM_VDD	power	DDRM_VDD	I	–	–	–	–	–	–	–
Note: I/Os for each peripheral are grouped into I/O sets, listed in the column "I/O Set". For all peripherals, use I/Os that belong to the same I/O set. Timings can be unpredictable when I/Os from different I/O sets are mixed. When using an I/O line with the Analog-to-Digital Converter (ADC) or with the Analog Comparator Controller (ACC), the PIO line configuration (pull-up, pull-down) programmed before assigning this line to the ADC or ACC peripheral is not modified by this peripheral. Refer to I/O Characteristics in the Electrical Characteristics section of the SAMA7D6 Series data sheet for the definition of I/Os. PU=Pull-Up, PD=Pull-Down, HiZ=High Impedance, ST=Schmitt Trigger This is the PIOBU state after VBAT power-up. If programmed to another value, this value is maintained as long as VBAT is not removed. Open-drain output requires an external resistor.