4.1 WPVS bit incorrect behavior
The EIC_WPSR.WPVS bit never rises to 1.
Work Around
None
Affected Silicon Revisions
| A0 | A1 | A1-D1G | A1-D2G | ||||
| X | X | X | X |
The EIC_WPSR.WPVS bit never rises to 1.
None
| A0 | A1 | A1-D1G | A1-D2G | ||||
| X | X | X | X |
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