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SAMA7G5 Series Silicon Errata and Data Sheet Clarifications
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SAMA7G54
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21
Controller Area Network (MCAN)
Scope
1
Silicon Issue Summary
2
ROM Code
3
Cortex-A7 Processor (Arm)
4
External Interrupt Controller (EIC)
5
DMA Controller (XDMAC)
6
Reset Controller (RSTC)
7
Real-time Clock (RTC)
8
Chip Identifier (CHIPID)
9
OTP Controller (OTPC)
10
Power Management Controller (PMC)
11
Parallel Input/Output Controller (PIO)
12
Analog-to-Digital Converter (ADC) Controller
13
Image Sensor Controller (ISC)
14
Synchronous Serial Controller (SSC)
15
Sony/Philips Digital Interface Receiver (SPDIFRX)
16
Advanced Encryption Standard (AES)
17
Security Module (SECUMOD)
18
Gigabit Ethernet MAC (GMAC)
19
Flexible Serial Communication Controller (FLEXCOM)
20
Secure Digital MultiMedia Card Controller (SDMMC)
21
Controller Area Network (MCAN)
21.1
Edge filtering causes mis-synchronization when falling edge at Rx input pin coincides with end of integration phase
21.2
Configuration of MCAN_NBTP.NTSEG2 = ’0’ not allowed
21.3
Retransmission in DAR mode due to lost arbitration at the first two identifier bits
21.4
Tx FIFO message sequence inversion
21.5
Unexpected High Priority Message (HPM) interrupt
21.6
Issue message transmitted with wrong arbitration and control fields
21.7
Debug message handling state machine not reset to Idle when CCCR.INIT is set
21.8
Message order inversion when transmitting from dedicated Tx buffers configured with same message ID
21.9
Frame transmitted despite confirmed transmit cancellation for CAN-FD messages with more than 8 data bytes
21.10
MCAN_TSU_TSCFG reset after read
21.11
MCAN_TSU_TSS1 not reset after a MCAN_TSU_TSx read
21.12
MCAN_TSU_ATB read resets the timebase value
22
Timer Counter (TC)
23
USB Device High Speed Port (UDPHS)
24
Low Power Modes
25
Data Sheet Clarifications
26
Revision History
Microchip Information
21 Controller Area Network (MCAN)
