1 Silicon Issue Summary

In this table and in subsequent sections, the following applies:

“X” means the device revision is affected by the erratum.
“–” means the device revision is not affected by the erratum.

Table 1-1. Silicon Issue Summary
Module	Erratum	Affected Device Revisions
Module	Erratum	A0	A1	A1-D1G	A1-D2G	A1-D4G
ROM Code	NAND Flash and Octal SPI boot not supported	X	X	X	X	X
ROM Code	Boot failure on e.MMC memories	X	X	X	X	X
Cortex-A7	PMU interrupt spurious rise	X	X	X	X	X
Cortex-A7	AXIERRIRQ interrupt spurious rise	X	X	X	X	X
EIC	WPVS bit incorrect behavior	X	X	X	X	X
XDMAC	Data corrupted when number of AXI outstanding transactions differs from 1	X	X	X	X	X
XDMAC	Some XDMAC0 and XDMAC1 channels ineffective	X	–	–	–	–
RSTC	RSTC_SR.RSTTYP not showing GENERAL_RST	X	X	X	X	X
RTC	RTC_TSTR0 timestamping error	X	X	X	X	X
CHIPID	CHIPID_EXID may report a wrong value	–	–	X	X	–
OTPC	OTPC limited number of packets	X	X	X	X	X
	OTPC restricted operating range in Write mode	X	X	X	X	X
	OTPC wrong default configuration	X	X	X	X	X
PMC	MCKRDY flag error	X	X	X	X	X
	Delay to first establish PCK	X	X	X	X	X
	PCK and GCLK Ready status issue	X	X	X	X	X
	Processor (CPU_CLK0) and main system bus clock (MCK0) source selection	X	X	X	X	X
PIO	Open drain management limitation	X	X	X	X	X
ADC	Spurious effect when zeros written to ADC_EOC_IDR	X	X	X	X	X
	EOC interrupts not disabled when ones written to ADC_EOC_IDR	X	X	X	X	X
	ADC_IMR interrupts enabled when ones written to ADC_EOC_IDR	X	X	X	X	X
	Temperature sensor still enabled when stopped without conversion	X	X	X	X	X
	Temperature sensor spurious activation with CH30	X	X	X	X	X
	Sleep mode ineffective	X	X	X	X	X
ISC	Spurious DMA descriptor writing	X	X	X	X	X
	Incoming pixels corrupted after overload	X	X	X	X	X
	Frequency limitation	X	–	–	–	–
SSC	Inverted left/right channels	X	X	X	X	X
SSC	TD output delay	X	X	X	X	X
SPDIFRX	SPDIFRX left/right inversion	X	X	X	X	X
AES	SPLIP mode does not work with some header sizes	X	X	X	X	X
SECUMOD	Dynamic detection intrusion (PIOBU) alarm issue	X	X	X	X	X
	Tamper timestamping polarity error	X	X	X	X	X
	SECUMOD registers BMPR and WKPR reading issue	X	X	X	X	X
GMAC	GMAC0 not functional with multiple queues in 10/100 Half Duplex mode	X	X	X	X	X
	Incorrect reading of Specific Address filter registers on GMAC0 and GMAC1	X	–	–	–	–
	Incorrect reading of Type 1 Screener registers on GMAC0 and GMAC1	X	–	–	–	–
	Incorrect reading of Type 2 Screener registers on GMAC0 and GMAC1	X	–	–	–	–
	GTSUCOMP ineffective connection to TC1	X	X	X	X	X
FLEXCOM	Write Protection ineffective on FLEXCOM8 to FLEXCOM11	X	X	X	X	X
SDMMC	SDMMC failure when changing speed mode or performing ALL soft reset on the fly	X	X	X	X	X
	SDR104, HS200, HS400 modes are not functional	X	X	X	X	X
	GCLK cannot be stopped	X	X	X	X	X
	SDHC blocked after switch from high-speed mode	X	X	X	X	X
MCAN	Edge filtering causes mis-synchronization when falling edge at Rx input pin coincides with end of integration phase	X	X	X	X	X
	Configuration of MCAN_NBTP.NTSEG2 = ’0’ not allowed	X	X	X	X	X
	Retransmission in DAR mode due to lost arbitration at the first two identifier bits	X	X	X	X	X
	Tx FIFO message sequence inversion	X	X	X	X	X
	Unexpected High Priority Message (HPM) interrupt	X	X	X	X	X
	Issue message transmitted with wrong arbitration and control fields	X	X	X	X	X
	Debug message handling state machine not reset to Idle when CCCR.INIT is set	X	X	X	X	X
	Message order inversion when transmitting from dedicated Tx buffers configured with same message ID	X	X	X	X	X
	Frame transmitted despite confirmed transmit cancellation for CAN-FD messages with more than 8 data bytes	X	X	X	X	X
	MCAN_TSU_TSCFG reset after read	X	X	X	X	X
	MCAN_TSU_TSS1 not reset after a MCAN_TSU_TSx read	X	X	X	X	X
	MCAN_TSU_ATB read resets the timebase value	X	X	X	X	X
TC	TC0 Channel 2 registers incorrect reading	X	–	–	–	–
UDPHS	EHCI spurious stop when Suspend mode occurs on port A	X	X	X	X	X
Low Power Modes	ULP2 mode does not work	X	X	X	X	X