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SAMA7G5 Series Silicon Errata and Data Sheet Clarifications
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SAMA7G54
SAMA7G54D1G
SAMA7G54D2G
SAMA7G54D4G
Scope
1
Silicon Issue Summary
2
ROM Code
2.1
NAND Flash and Octal SPI boot not supported
2.2
Boot failure on e.MMC memories
3
Cortex-A7 Processor (Arm)
3.1
PMU interrupt spurious rise
3.2
AXIERRIRQ interrupt spurious rise
4
External Interrupt Controller (EIC)
4.1
WPVS bit incorrect behavior
5
DMA Controller (XDMAC)
5.1
Data corrupted when number of AXI outstanding transactions differs from 1
5.2
Some XDMAC0 and XDMAC1 channels ineffective
6
Reset Controller (RSTC)
6.1
RSTC_SR.RSTTYP not showing GENERAL_RST
7
Real-time Clock (RTC)
7.1
RTC_TSTR0 timestamping error
8
Chip Identifier (CHIPID)
8.1
CHIPID_EXID may report a wrong value
9
OTP Controller (OTPC)
9.1
OTPC limited number of packets
9.2
OTPC restricted operating range in Write mode
9.3
OTPC wrong default configuration
10
Power Management Controller (PMC)
10.1
MCKRDY flag error
10.2
Delay to first establish PCK
10.3
PCK and GCLK Ready status issue
10.4
Processor (CPU_CLK
0
) and main system bus clock (MCK
0
) source selection
11
Parallel Input/Output Controller (PIO)
11.1
Open drain management limitation
12
Analog-to-Digital Converter (ADC) Controller
12.1
Spurious effect when zeros written to ADC_EOC_IDR
12.2
EOC interrupts not disabled when ones written to ADC_EOC_IDR
12.3
ADC_IMR interrupts enabled when ones written to ADC_EOC_IDR
12.4
Temperature sensor still enabled when stopped without conversion
12.5
Temperature sensor spurious activation with CH30
12.6
Sleep mode ineffective
13
Image Sensor Controller (ISC)
13.1
Spurious DMA descriptor writing
13.2
Incoming pixels corrupted after overload
13.3
Frequency limitation
14
Synchronous Serial Controller (SSC)
14.1
Inverted left/right channels
14.2
TD output delay
15
Sony/Philips Digital Interface Receiver (SPDIFRX)
15.1
SPDIFRX left/right inversion
16
Advanced Encryption Standard (AES)
16.1
SPLIP mode does not work with some header sizes
17
Security Module (SECUMOD)
17.1
Dynamic detection intrusion (PIOBU) alarm issue
17.2
Tamper timestamping polarity error
17.3
SECUMOD registers BMPR and WKPR reading issue
18
Gigabit Ethernet MAC (GMAC)
18.1
GMAC0 not functional with multiple queues in 10/100 Half Duplex mode
18.2
Incorrect reading of Specific Address filter registers on GMAC0 and GMAC1
18.3
Incorrect reading of Type 1 Screener registers on GMAC0 and GMAC1
18.4
Incorrect reading of Type 2 Screener registers on GMAC0 and GMAC1
18.5
GTSUCOMP ineffective connection to TC1
19
Flexible Serial Communication Controller (FLEXCOM)
19.1
Write Protection ineffective on FLEXCOM8 to FLEXCOM11
20
Secure Digital MultiMedia Card Controller (SDMMC)
20.1
SDMMC failure when changing speed mode or performing ALL soft reset on the fly
20.2
SDR104, HS200, HS400 modes are not functional
20.3
GCLK cannot be stopped
20.4
SDHC blocked after switch from high-speed mode
21
Controller Area Network (MCAN)
21.1
Edge filtering causes mis-synchronization when falling edge at Rx input pin coincides with end of integration phase
21.2
Configuration of MCAN_NBTP.NTSEG2 = ’0’ not allowed
21.3
Retransmission in DAR mode due to lost arbitration at the first two identifier bits
21.4
Tx FIFO message sequence inversion
21.5
Unexpected High Priority Message (HPM) interrupt
21.6
Issue message transmitted with wrong arbitration and control fields
21.7
Debug message handling state machine not reset to Idle when CCCR.INIT is set
21.8
Message order inversion when transmitting from dedicated Tx buffers configured with same message ID
21.9
Frame transmitted despite confirmed transmit cancellation for CAN-FD messages with more than 8 data bytes
21.10
MCAN_TSU_TSCFG reset after read
21.11
MCAN_TSU_TSS1 not reset after a MCAN_TSU_TSx read
21.12
MCAN_TSU_ATB read resets the timebase value
22
Timer Counter (TC)
22.1
TC0 Channel 2 registers incorrect reading
23
USB Device High Speed Port (UDPHS)
23.1
EHCI spurious stop when Suspend mode occurs on port A
24
Low Power Modes
24.1
ULP2 mode does not work
25
Data Sheet Clarifications
26
Revision History
26.1
DS80001016F - 06/2025
26.2
DS80001016E - 03/2025
26.3
DS80001016D - 11/2024
26.4
DS80001016C - 12/2023
26.5
DS80001016B - 08/2022
26.6
DS80001016A - 03/2022
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