45.4 Signal Interface
The ETH Controller module includes the following signal interfaces:
- RMII to an external PHY
- MDIO interface for external PHY management
- Client APB interface for accessing ETH registers
- Host AHB interface for memory access
- TSUCOMP signal for TSU timer count value comparison
| Signal Name | Function | RMII |
|---|---|---|
| ETH_TXCK1(1) | Transmit Clock or Reference Clock | REFCK |
| ETH_TXEN | Transmit Enable | TXEN |
| Tx[1:0] and Rx[1:0] | Transmit Data | TXD[1:0] |
| ETH_TXER | Transmit Coding Error | Not Used |
| ETH_RXCK | Receive Clock | Not Used |
| ETH_RXDV | Receive Data Valid | CRSDV |
| Tx[1:0] and Rx[1:0] | Receive Data | RXD[1:0] |
| ETH_RXER | Receive Error | RXER |
| ETH_CRS | Carrier Sense and Data Valid | Not Used |
| ETH_COL | Collision Detect | Not Used |
| ETH_MDC | Management Data Clock | MDC |
| ETH_MDIO | Management Data Input/Output | MDIO |
Note:
- Input only. ETH_TXCK1 must be provided with a 50 MHz clock for RMII interfaces, respectively.