49.32 Quadrature Encoder Interface AC Electrical Specifications

Table 49-41. Quadrature Encoder Interface AC Electrical Specifications
AC CharacteristicsStandard Operating Conditions: VDD33 = VDDIO = AVDD = 1.9–3.6V (Unless Otherwise Stated)

Operating Temperature:

-40°C ≤ TA ≤ +125°C for Extended Temperature

Parameter NumberSymbolCharacteristicsMin.Typ.Max.UnitsConditions
PDEC_1TtPHTQCK high time1.5/fGCLK_QEI— —nsVDDIOx(minimum) to VDDIOx(maximum)
PDEC_3TtPLTQCK low time1.5/fGCLK_QEI——ns
PDEC_5TtPPTQCK input period3/fGCLK_QEI——ns
PDEC_7TCKEXTDLYDelay from External TxCK Clock Edge to counter Increment —5/fGCLK_QEIns
PDEC_11TPDHQE Input High Time (Digital Filter Disabled)6/fGCLK_QEI——ns
QE Input High Time (Digital Filter Enabled)6*N/fGCLK_QEI——nsN = 1, 2, 4, 8, 16, 32, 64, 128
PDEC_13TPDLQE Input Low Time (Digital Filter Disabled)6/fGCLK_QEI——ns —
QE Input Low Time (Digital Filter Enabled)6*N/fGCLK_QEI——nsN = 1, 2, 4, 8, 16, 32, 64, 128
PDEC_15TPDINQE Input Period (Digital Filter Disabled)12/fGCLK_QEI——ns —
QE Input Period (Digital Filter Enabled)12*N/fGCLK_QEI——nsN = 1, 2, 4, 8, 16, 32, 64, 128
PDEC_17TPDPQE Phase Period (Digital Filter Disabled)3/fGCLK_QEI——ns
QE Phase Period (Digital Filter Enabled)3*N/fGCLK_QEI——nsN = 1, 2, 4, 8, 16, 32, 64, 128
PDEC_19TPDIDXIndex Pulse Width, Digital Filter Disabled3/fGCLK_QEI—15/fGCLK_QEIns —
Index Pulse Width, Digital Filter Enabled3*N/fGCLK_QEI—15×N/fGCLK_QEInsN = 1, 2, 4, 8, 16, 32, 64, 128
PDEC_21TPDFHFilter Time to Recognize High, with Digital Filter6/fGCLK_QEI——ns —
PDEC_23TPDFLFilter Time to Recognize Low, with Digital Filter6/fGCLK_QEI——ns —
PDEC_24fGCLK_QEICLK_QEI ——FCLK_41MHz —
Figure 49-32. Quadrature Encoder (QEI) Counter Mode AC Timing Diagram
Figure 49-33. Quadrature Encoder (QEI) Input AC Timing Diagram