49.23 I²C Module Electrical Specifications

Table 49-30. I²C Module Host Mode Electrical Specifications
AC Characteristics				Standard Operating Conditions: VDD33 = VDDIO = AVDD = 1.9–3.6V (Unless Otherwise Stated) Operating Temperature: -40°C ≤ TA ≤ +125°C for Extended Temperature
Parameter Number	Symbol	Characteristics		Min.	Max.	Units	Conditions
I2CM_1	TL0:SCL	Host Clock Low Time	100 kHz mode	4.7	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			400 kHz mode	1.3	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			1 MHz mode	0.5	—	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, C_LOAD = 550 pF
I2CM_3	THI:SCL	Host Clock High Time	100 kHz mode	4	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			400 kHz mode	0.6	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			1 MHz mode	0.26	—	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, C_LOAD = 550 pF
I2CM_5	TF:SCL	SDAx and SCLx Fall Time	100 kHz mode	—	300	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			400 kHz mode	20 + (VDDIO/5.5)	300	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF. REXT × C_LOAD > T_fall (minimum). REXT is external series resistor to be added to the I2C pin and must not exceed 1 kΩ.
			1 MHz mode	20 + (VDDIO/5.5)	120	ns	VDDIOx = 3.3V, I_PULL-UP = 20 mA, C_LOAD = 550 pF. REXT × C_LOAD > T_fall (minimum). REXT is external series resistor to be added to the I2C pin and must not exceed 1 kΩ.
I2CM_7	TR:SCL	SDAx and SCLx Rise Time	100 kHz mode	—	1000	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			400 kHz mode	—	300	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			1 MHz mode	—	120	ns	VDDIOx = 3.3V, I_PULL-UP = 20 mA, C_LOAD = 550 pF.
I2CM_9	TSU:DAT	Data Setup Time	100 kHz mode	250	—	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			400 kHz mode	100	—	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			1 MHz mode	50	—	ns	VDDIOx = 3.3V, I_PULL-UP = 20 mA, C_LOAD = 550 pF
I2CM_11	THD:DAT	Data Hold Time ⁽¹⁾	100 kHz mode	300	—	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			400 kHz mode	300	—	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			1 MHz mode	0	—	ns	VDDIOx = 3.3V, I_PULL-UP = 20 mA, C_LOAD = 550 pF
I2CM_13	TSU:STA	Start Condition Setup Time	100 kHz mode	4.7	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			400 kHz mode	0.6	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			1 MHz mode	0.26	—	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, C_LOAD = 550 pF
I2CM_15	THD:STA	Start Condition Hold Time	100 kHz mode	4	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			400 kHz mode	0.6	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			1 MHz mode	0.26	—	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, C_LOAD = 550 pF
I2CM_17	TSU:ST0	Stop Condition Setup Time	100 kHz mode	4	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			400 kHz mode	0.6	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			1 MHz mode	0.26	—	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, C_LOAD = 550 pF
I2CM_21	TAA:SCL	Output Valid from Clock	100 kHz mode	—	3.45	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			400 kHz mode	—	0.9	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			1 MHz mode	—	0.45	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, C_LOAD = 550 pF
I2CM_23	TBF:SDA	Bus Free Time ⁽²⁾	100 kHz mode	4.7	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			400 kHz mode	1.3	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, C_LOAD = 400 pF
			1 MHz mode	0.5	—	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, C_LOAD = 550 pF
Note: Longest delay between data hold timing based on CFGI2C.I2CDSEL for 100 kHz/400 kHz mode. The amount of time the bus must be free before a new transmission can start (STOP condition to START condition).

Figure 49-22. I²C Start/Stop Bits Host Mode AC Timing Diagram

Figure 49-23. I²C Bus Data Host Mode AC Timing Diagram

Table 49-31. I²C Module Client Mode Electrical Specifications
AC Characteristics				Standard Operating Conditions: VDD33 = VDDIO = AVDD = 1.9–3.6V (Unless Otherwise Stated) Operating Temperature: -40°C ≤ TA ≤ +125°C for Extended Temperature
Parameter Number	Symbol	Characteristics		Min.	Max.	Units	Conditions
I2CS_1	TL0:SCL	Client Clock Low Time	100 kHz mode	4.7	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			400 kHz mode	1.3	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			1 MHz mode	0.5	—	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, CLOAD = 550 pF
I2CS_3	THI:SCL	Client Clock High Time	100 kHz mode	4	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			400 kHz mode	0.6	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			1 MHz mode	0.26	—	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, CLOAD = 550 pF
I2CS_5	TF:SCL	SDAx and SCLx Fall Time	100 kHz mode	—	300	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF.
			400 kHz mode	20 + (VDDIO/5.5)	300	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF. REXT × CLOAD > T_fall (minimum). REXT is external series resistor to be added to the I2C pin and must not exceed 1 kΩ.
			1 MHz mode	20 + (VDDIO/5.5)	120	ns	VDDIOx = 3.3V, I_PULL-UP = 20 mA, CLOAD = 550 pF. REXT × CLOAD > T_fall (minimum). REXT is external series resistor to be added to the I2C pin and must not exceed 1 kΩ.
I2CS_7	TR:SCL	SDAx and SCLx Rise Time	100 kHz mode	—	1000	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			400 kHz mode	—	300	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			1 MHz mode	—	120	ns	VDDIOx = 3.3V, I_PULL-UP = 20 mA, CLOAD = 550 pF
I2CS_9	TSU:DAT	Data Setup Time	100 kHz mode	250	—	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			400 kHz mode	100	—	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			1 MHz mode	50	—	ns	VDDIOx = 3.3V, I_PULL-UP = 20 mA, CLOAD = 550 pF
I2CS_11	THD:DAT	Data Hold Time⁽¹⁾	100 kHz mode	300	—	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			400 kHz mode	300	—	ns	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			1 MHz mode	0	—	ns	VDDIOx = 3.3V, I_PULL-UP = 20 mA, CLOAD = 550 pF
I2CS_13	TSU:STA	Start Condition Setup Time	100 kHz mode	4.7	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			400 kHz mode	0.6	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			1 MHz mode	0.26	—	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, CLOAD = 550 pF
I2CS_15	THD:STA	Start Condition Hold Time	100 kHz mode	4	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			400 kHz mode	0.6	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			1 MHz mode	0.26	—	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, CLOAD = 550 pF
I2CS_17	TSU:ST0	Stop Condition Setup Time	100 kHz mode	4	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			400 kHz mode	0.6	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			1 MHz mode	0.26	—	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, CLOAD = 550 pF
I2CS_21	TAA:SCL	Output Valid from Clock	100 kHz mode	—	3.45	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			400 kHz mode	—	0.9	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			1 MHz mode	—	0.45	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, CLOAD = 550 pF
I2CS_23	TBF:SDA	Bus Free Time⁽¹⁾	100 kHz mode	4.7	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			400 kHz mode	1.3	—	µs	VDDIOx = 3.3V, I_PULL-UP = 3 mA, CLOAD = 400 pF
			1 MHz mode	0.5	—	µs	VDDIOx = 3.3V, I_PULL-UP = 20 mA, CLOAD = 550 pF
Note: Longest delay between data hold timing based on CFGI2C.I2CDSEL for 100 kHz/400 kHz mode. The amount of time the bus must be free before a new transmission can start (STOP condition to START condition).

Figure 49-24. I²C Start/Stop Bits Client Mode AC Timing Diagram

Figure 49-25. I²C Bus Data Client Mode AC Timing Diagram

49.23 I2C Module Electrical Specifications

49.23 I²C Module Electrical Specifications