18.5 Register Summary

See CRU module in the Product Memory Mapping Overview from Related Links for base address.

Note: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET and INV Registers from Related Links


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	OSCCON	7:0	CLKLOCK			SLPEN	CF		SOSCEN	OSWEN
		15:8	COSC[3:0]				NOSC[3:0]
		23:16	DRMEN		2SPDSLP
		31:24						FRCDIV[2:0]
0x04	OSCTRIM	7:0			TUN[5:0]
		15:8
		23:16
		31:24
0x08	SPLLCON	7:0				SPLLFLOCK	SPLLPWDN
		15:8	SPLL1POSTDIV1[7:0]
		23:16					SPLL2POSTDIV2[3:0]
		31:24	SPLL_BYP[1:0]
0x0C	UPLLCON	7:0	UPLLPOSTDIV1[3:0]				UPLLPWDN	UPLLBSWSEL[2:0]
		15:8	UPLLFBDIV[3:0]				UPLLRST	UPLLFLOCK	UPLLPOSTDIV1[5:4]
		23:16	UPLLREFDIV[1:0]		UPLLFBDIV[9:4]
		31:24	UPLL_BYP				UPLLREFDIV[5:2]
0x10	EPLLCON	7:0	EPLLPOSTDIV1[3:0]				EPLLPWDN	EPLLBSWSEL[2:0]
		15:8	EPLLFBDIV[3:0]				EPLLRST	EPLLFLOCK	EPLLPOSTDIV1[5:4]
		23:16	EPLLREFDIV[1:0]		EPLLFBDIV[9:4]
		31:24	EPLL_BYP			ECLKOUTEN	EPLLREFDIV[5:2]
0x14	APLLCON	7:0			EPLLPOSTDIV2[5:0]
		15:8
		23:16
		31:24
0x18	RCON	7:0	EXTR	SWR	DMTO	WDTO	SLEEP	IDLE	BOR	POR
		15:8						DPSLP	CMR
		23:16							VBPOR	VBAT
		31:24	POR_IO	POR_CORE			BCFGERR	BCFGFAIL	NVMLTA	NVMEOL
0x1C	RSWRST	7:0								SWRST
		15:8
		23:16
		31:24
0x20	RNMICON	7:0	NMICNT[7:0]
		15:8	NMICNT[15:8]
		23:16	SWNMI				EXT	PLVD	CF	WDTS
		31:24							DMTO	WDTR
0x24 ... 0x27	Reserved
0x28	REFO1CON	7:0					ROSEL3	ROSEL2	ROSEL1	ROSEL0
		15:8	ON	FRZ	SIDL	OE	RSLP		DIVSW_EN	ACTIVE
		23:16	RODIV7	RODIV6	RODIV5	RODIV4	RODIV3	RODIV2	RODIV1	RODIV0
		31:24		RODIV14	RODIV13	RODIV12	RODIV11	RODIV10	RODIV9	RODIV8
0x2C	REFO1TRIM	7:0
		15:8
		23:16	ROTRIM8
		31:24	ROTRIM0	ROTRIM1	ROTRIM2	ROTRIM3	ROTRIM4	ROTRIM5	ROTRIM6	ROTRIM7
0x30	REFO2CON	7:0					ROSEL3	ROSEL2	ROSEL1	ROSEL0
		15:8	ON	FRZ	SIDL	OE	RSLP		DIVSW_EN	ACTIVE
		23:16	RODIV7	RODIV6	RODIV5	RODIV4	RODIV3	RODIV2	RODIV1	RODIV0
		31:24		RODIV14	RODIV13	RODIV12	RODIV11	RODIV10	RODIV9	RODIV8
0x34	REFO2TRIM	7:0
		15:8
		23:16	ROTRIM8
		31:24	ROTRIM0	ROTRIM1	ROTRIM2	ROTRIM3	ROTRIM4	ROTRIM5	ROTRIM6	ROTRIM7
0x38	REFO3CON	7:0					ROSEL3	ROSEL2	ROSEL1	ROSEL0
		15:8	ON	FRZ	SIDL	OE	RSLP		DIVSW_EN	ACTIVE
		23:16	RODIV7	RODIV6	RODIV5	RODIV4	RODIV3	RODIV2	RODIV1	RODIV0
		31:24		RODIV14	RODIV13	RODIV12	RODIV11	RODIV10	RODIV9	RODIV8
0x3C	REFO3TRIM	7:0
		15:8
		23:16	ROTRIM8
		31:24	ROTRIM0	ROTRIM1	ROTRIM2	ROTRIM3	ROTRIM4	ROTRIM5	ROTRIM6	ROTRIM7
0x40	REFO4CON	7:0					ROSEL3	ROSEL2	ROSEL1	ROSEL0
		15:8	ON	FRZ	SIDL	OE	RSLP		DIVSW_EN	ACTIVE
		23:16	RODIV7	RODIV6	RODIV5	RODIV4	RODIV3	RODIV2	RODIV1	RODIV0
		31:24		RODIV14	RODIV13	RODIV12	RODIV11	RODIV10	RODIV9	RODIV8
0x44	REFO4TRIM	7:0
		15:8
		23:16	ROTRIM8
		31:24	ROTRIM0	ROTRIM1	ROTRIM2	ROTRIM3	ROTRIM4	ROTRIM5	ROTRIM6	ROTRIM7
0x48	REFO5CON	7:0					ROSEL3	ROSEL2	ROSEL1	ROSEL0
		15:8	ON	FRZ	SIDL	OE	RSLP		DIVSW_EN	ACTIVE
		23:16	RODIV7	RODIV6	RODIV5	RODIV4	RODIV3	RODIV2	RODIV1	RODIV0
		31:24		RODIV14	RODIV13	RODIV12	RODIV11	RODIV10	RODIV9	RODIV8
0x4C	REFO5TRIM	7:0
		15:8
		23:16	ROTRIM8
		31:24	ROTRIM0	ROTRIM1	ROTRIM2	ROTRIM3	ROTRIM4	ROTRIM5	ROTRIM6	ROTRIM7
0x50	REFO6CON	7:0					ROSEL3	ROSEL2	ROSEL1	ROSEL0
		15:8	ON	FRZ	SIDL	OE	RSLP		DIVSW_EN	ACTIVE
		23:16	RODIV7	RODIV6	RODIV5	RODIV4	RODIV3	RODIV2	RODIV1	RODIV0
		31:24		RODIV14	RODIV13	RODIV12	RODIV11	RODIV10	RODIV9	RODIV8
0x54	REFO6TRIM	7:0
		15:8
		23:16	ROTRIM8
		31:24	ROTRIM0	ROTRIM1	ROTRIM2	ROTRIM3	ROTRIM4	ROTRIM5	ROTRIM6	ROTRIM7
0x58	PB1DIV	7:0		PB1DIV[6:0]
		15:8	PB1DIVON				PB1DIVRDY
		23:16
		31:24
0x5C	PB2DIV	7:0		PB2DIV[6:0]
		15:8	PB2DIVON				PB2DIVRDY
		23:16
		31:24
0x60	PB3DIV	7:0		PB3DIV[6:0]
		15:8	PB3DIVON				PB3DIVRDY
		23:16
		31:24
0x64	PB4DIV	7:0		PB4DIV[6:0]
		15:8	PB4DIVON				PB4DIVRDY
		23:16
		31:24
0x68	PB5DIV	7:0		PB5DIV[6:0]
		15:8	PB5DIVON				PB5DIVRDY
		23:16
		31:24
0x6C	SLEWCON	7:0						SLW_UP	SLW_DN	SLW_BUSY
		15:8						SLW_DIV[2:0]
		23:16					SYS_DIV[3:0]
		31:24					SLW_DELAY[3:0]
0x70	CLKSTAT	7:0	SPLLRDY	UPLLRDY	EPLL2RDY	LPRCRDY	SOSCRDY	POSCRDY	SPLL1RDY	FRCRDY
		15:8						PB1RDY	SYSRDY	EPLL1RDY
		23:16
		31:24
0x74 ... 0x77	Reserved
0x78	CLK_DIAG	7:0		UPLL_STOP	EPLL_STOP	SPLL1_STOP	LPRC_STOP	FRC_STOP	SOSC_STOP	POSC_STOP
		15:8
		23:16	NMICTR7	NMICTR6	NMICTR5	NMICTR4	NMICTR3	NMICTR2	NMICTR1	NMICTR0
		31:24	NMICTR15	NMICTR14	NMICTR13	NMICTR12	NMICTR11	NMICTR10	NMICTR9	NMICTR8