38.6 Register Summary

See the CVD module in the Product Memory Mapping Overview from Related Links for the base address.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	CVDCON	7:0			CLKSEL[1:0]		TRIGSEL[3:0]
		15:8	FIFOTH[7:0]
		23:16	THSTR				CVDIEN	FIFOIEN	FIFOTH[9:8]
		31:24	ON	FRZ	SIDL	ORDER	SDWREN		ABORT	SWTRIG
0x04	CVDADC	7:0					ADCCON	ADCCON[2:0]
		15:8					ADCCON	ADCCON	ADCCON[1:0]
		23:16
		31:24
0x08	CVDSTAT	7:0		SD2INT	SD2DONE	SD2BUSY		SD1INT	SD1DONE	SD1BUSY
		15:8		SD4INT	SD4DONE	SD4BUSY		SD3INT	SD3DONE	SD3BUSY
		23:16	FIFOCNT[7:0]
		31:24	FIFOFULL	FIFOWM	FIFOMT				FIFOCNT[9:8]
0x0C ... 0x0F	Reserved
0x10	CVDRESH	7:0	POS[7:0]
		15:8	POS[15:8]
		23:16	POS[23:16]
		31:24
0x14	CVDRESL	7:0	NEG[7:0]
		15:8	NEG[15:8]
		23:16	NEG[23:16]
		31:24
0x18	CVDRESD	7:0	DELTA[7:0]
		15:8	DELTA[15:8]
		23:16	RXINDEX[4:0]						DELTA[17:16]
		31:24	TXINDEX[4:0]						SDNUM[1:0]
0x1C ... 0x7F	Reserved
0x80	CVDRX0	7:0			RXAN1[5:0]
		15:8			RXAN2[5:0]
		23:16			RXAN3[5:0]
		31:24			RXAN4[5:0]
0x84	CVDRX1	7:0			RXAN5[5:0]
		15:8			RXAN6[5:0]
		23:16			RXAN7[5:0]
		31:24			RXAN8[5:0]
0x88	CVDRX2	7:0			RXAN9[5:0]
		15:8			RXAN10[5:0]
		23:16			RXAN11[5:0]
		31:24			RXAN12[5:0]
0x8C	CVDRX3	7:0			RXAN13[5:0]
		15:8			RXAN14[5:0]
		23:16			RXAN15[5:0]
		31:24			RXAN16[5:0]
0x90	CVDRX4	7:0			RXAN17[5:0]
		15:8			RXAN18[5:0]
		23:16
		31:24
0x94 ... 0xBF	Reserved
0xC0	CVDTX0	7:0			TXOUT0[5:0]
		15:8			TXOUT1[5:0]
		23:16			TXOUT2[5:0]
		31:24			TXOUT3[5:0]
0xC4	CVDTX1	7:0			TXOUT4[5:0]
		15:8			TXOUT5[5:0]
		23:16			TXOUT6[5:0]
		31:24			TXOUT7[5:0]
0xC8	CVDTX2	7:0			TXOUT8[5:0]
		15:8			TXOUT9[5:0]
		23:16			TXOUT10[5:0]
		31:24			TXOUT11[5:0]
0xCC	CVDTX3	7:0			TXOUT12[5:0]
		15:8			TXOUT13[5:0]
		23:16			TXOUT14[5:0]
		31:24			TXOUT15[5:0]
0xD0	CVDTX4	7:0			TXOUT16[5:0]
		15:8			TXOUT17[5:0]
		23:16
		31:24
0xD4 ... 0xFF	Reserved
0x0100	CVDSD0C1	7:0		SD0OVRSAMP[6:0]
		15:8	SD0TH[7:0]
		23:16	SD0TH[15:8]
		31:24	SD0TH[23:16]
0x0104	CVDSD0C2	7:0	SD0RXSTRIDE	SD0RXSTRIDE	SD0RXBEG[5:0]
		15:8	SD0RXSTRIDE	SD0RXSTRIDE	SD0RXEND[5:0]
		23:16	SD0TXSTRIDE	SD0TXSTRIDE	SD0TXBEG[5:0]
		31:24	SD0TXSTRIDE	SD0TXSTRIDE	SD0TXEND[5:0]
0x0108	CVDSD0C3	7:0		SD0CHGTIME[6:0]
		15:8		SD0ACQTIME[6:0]
		23:16	SDnADCCON[7:0]
		31:24	SD0EN[1:0]				SD0BUF	SD0INTEN	SD0SELF	SD0MUT
0x010C	CVDSD0T2	7:0		SD0CONTIME[6:0]
		15:8		SD0POLTIME[6:0]
		23:16		SD0OVRTIME[6:0]
		31:24		SD0CHNTIME[6:0]
0x0110	CVDSD1C1	7:0		SD1OVRSAMP[6:0]
		15:8	SD1TH[7:0]
		23:16	SD1TH[15:8]
		31:24	SD1TH[23:16]
0x0114	CVDSD1C2	7:0	SD1RXSTRIDE	SD1RXSTRIDE	SD1RXBEG[5:0]
		15:8	SD1RXSTRIDE	SD1RXSTRIDE	SD1RXEND[5:0]
		23:16	SD1TXSTRIDE	SD1TXSTRIDE	SD1TXBEG[5:0]
		31:24	SD1TXSTRIDE	SD1TXSTRIDE	SD1TXEND[5:0]
0x0118	CVDSD1C3	7:0		SD1CHGTIME[6:0]
		15:8		SD1ACQTIME[6:0]
		23:16					CVDEN	CVDCPL[2:0]
		31:24	SD1EN[1:0]				SD1BUF	SD1INTEN	SD1SELF	SD1MUT
0x011C	CVDSD1T2	7:0		SD1CONTIME[6:0]
		15:8		SD1POLTIME[6:0]
		23:16		SD1OVRTIME[6:0]
		31:24		SD1CHNTIME[6:0]
0x0120	CVDSD2C1	7:0		SD2OVRSAMP[6:0]
		15:8	SD2TH[7:0]
		23:16	SD2TH[15:8]
		31:24	SD2TH[23:16]
0x0124	CVDSD2C2	7:0	SD2RXSTRIDE	SD2RXSTRIDE	SD2RXBEG[5:0]
		15:8	SD2RXSTRIDE	SD2RXSTRIDE	SD2RXEND[5:0]
		23:16	SD2TXSTRIDE	SD2TXSTRIDE	SD2TXBEG[5:0]
		31:24	SD2TXSTRIDE	SD2TXSTRIDE	SD2TXEND[5:0]
0x0128	CVDSD2C3	7:0		SD2CHGTIME[6:0]
		15:8		SD2ACQTIME[6:0]
		23:16					CVDEN	CVDCPL[2:0]
		31:24	SD2EN[1:0]				SD2BUF	SD2INTEN	SD2SELF	SD2MUT
0x012C	CVDSD2T2	7:0		SD2CONTIME[6:0]
		15:8		SD2POLTIME[6:0]
		23:16		SD2OVRTIME[6:0]
		31:24		SD2CHNTIME[6:0]
0x0130	CVDSD3C1	7:0		SD3OVRSAMP[6:0]
		15:8	SD3TH[7:0]
		23:16	SD3TH[15:8]
		31:24	SD3TH[23:16]
0x0134	CVDSD3C2	7:0	SD3RXSTRIDE	SD3RXSTRIDE	SD3RXBEG[5:0]
		15:8	SD3RXSTRIDE	SD3RXSTRIDE	SD3RXEND[5:0]
		23:16	SD3TXSTRIDE	SD3TXSTRIDE	SD3TXBEG[5:0]
		31:24	SD3TXSTRIDE	SD3TXSTRIDE	SD3TXEND[5:0]
0x0138	CVDSD3C3	7:0		SD3CHGTIME[6:0]
		15:8		SD3ACQTIME[6:0]
		23:16					CVDEN	CVDCPL[2:0]
		31:24	SD3EN[1:0]				SD3BUF	SD3INTEN	SD3SELF	SD3MUT
0x013C	CVDSD3T2	7:0		SD3CONTIME[6:0]
		15:8		SD3POLTIME[6:0]
		23:16		SD3OVRTIME[6:0]
		31:24		SD3CHNTIME[6:0]