49.12 Maximum Clock Frequencies Electrical Specifications
| AC Characteristics | Standard Operating Conditions: VDD33 = VDDIO =
AVDD = 1.9–3.6V (Unless Otherwise Stated) Operating Temperature: -40°C ≤ TA ≤ +125°C for Extended Temperature | |||
|---|---|---|---|---|
| Parameter Number | Symbol | Characteristics | Max | Units |
| FCLK_1 | FCY | MCU clock frequency | 128 | MHz |
| FCLK_3 | fAHB | AHB clock frequency | 128 | MHz |
| FCLK_5a | fAPBn | PB1, PB2, PB4 clock frequency | 128 | MHz |
| FCLK_5b | fAPBn | PB3 clock frequency | 8 | MHz |
| FCLK_5b | fAPBn | PB5 clock frequency | 64 | MHz |
| FCLK_6 | fREFO[0:5] | Reference clock frequency | 128 | MHz |
| FCLK_7a | fSPLL1 | SPLL1 clock frequency | 128 | MHz |
| FCLK_9a | fEPLL1 | EPLL clock frequency | 50 | MHz |
| FCLK_9b | fEPLL2 | EPLL clock frequency | 80 | MHz |
| FCLK_11a | fUPLL | UPLL clock frequency | 96 | MHz |
| FCLK_13 | fGCLK_EIC | EIC input clock frequency | 128 | MHz |
| FCLK_15 | fGCLK_FREQM_MSR | FREQM Measure clock frequency | 128 | MHz |
| FCLK_17 | fGCLK_FREQM_REF | FREQM Reference clock frequency | 64 | MHz |
| FCLK_19 | fGCLK_EVSYS_CHANNELx | EVSYS channel x input clock frequency | 128 | MHz |
| FCLK_21 | fGCLK_SERCOMx_SLOW | Common SERCOM slow input clock frequency | 32 | khz |
| FCLK_23 | fGCLK_SERCOMx_CORE | SERCOMx input clock frequency | 128 | MHz |
| FCLK_25 | fGCLK_CANx | CAN input clock frequency (SPLL) | 128 | MHz |
| FCLK_25a | CAN input clock frequency (EPLL2) | 80 | MHz | |
| FCLK_27 | f_USB | USB input clock frequency | 48 | MHz |
| FCLK_35 | fGCLK_TCCx | TCCx input clock frequency | 128 | MHz |
| FCLK_37 | fGCLK_TCx | TCx input clock frequency | 128 | MHz |
| FCLK_41 | fGCLK_QEI | QEI input clock frequency | 128 | MHz |
| FCLK_43 | fGCLK_CCL | CCL input clock frequency | 128 | MHz |
| FCLK_45a | fREFI | External REFO input clock frequency | 64 | MHz |
| FCLK_49 | fGCLK_AC | Analog comparator peripheral module clock frequency | 128 | MHz |
| FCLK_51 | f_ADCx | ADC Controller clock frequency | 64 | MHz |
| FCLK_53 | f_DAC | DAC Controller input clock frequency | 128 | MHz |
| FCLK_56 | fGCLK_CVD | CVD input clock frequency | 64 | MHz |
| FCLK_61 | f_ETH | Ethernet input clock frequency | 50 | MHz |
| FCLK_61a | fGCLK_ETH_TSU | Ethernet Time-Stamping Unit Clock | 128 | MHz |
| FCLK_67 | fGCLK_SPI | SERCOM SPI internal GCLK frequency | 128 | MHz |
| FCLK_69 | fGCLK_I2C | SERCOM I2C internal GCLK frequency | 128 | MHz |
| FCLK_71 | fGCLK_USART | SERCOM USART internal GCLK frequency (Asynchronous Mode) | 128 | MHz |
| SERCOM USART internal GCLK frequency (Synchronous Mode, DIRECT pin) | 128 | MHz | ||
| SERCOM USART internal GCLK frequency (Synchronous Mode, PPS pin) | 128 | MHz | ||
| FCLK_73 | fXCK_USART | SERCOM USART external XCK frequency (Asynchronous Mode, DIRECT) | 64 | MHz |
| SERCOM USART external XCK freq (Asynchronous Mode, PPS) | 32 | MHz | ||
| SERCOM USART external XCK freq (Synchronous Mode, DIRECT pin) | 16 | MHz | ||
| SERCOM USART external XCK freq (Synchronous Mode, PPS pin) | 10.67 | MHz | ||
|
Note: To achieve reliable IEEE® 1588
function, fGCLK_ETH_TSU must be less than the fAHB clock.
| ||||