18.6 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description.
Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description.
Some registers are enable-protected, meaning the user can only write them by disabling the peripheral. Enable protection is denoted by the Enable-Protected property in each individual register description.
The following are the list of conventions available in the register description:
- R = Readable bit
- W = Writable bit
- U = Unimplemented bit, read as ‘
0’ - -n = Value at POR
1= Bit is set0= Bit is cleared- x = Bit is unknown
- L = Lockable bit
- HS = Hardware Set
- HC = Hardware Cleared