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Highly Integrated Wireless MCU with CAN FD, Ethernet, USB, Motor Control, Graphics, Touch and Enhanced Security
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PIC32CX2051BZ62132
PIC32WM-BZ6204UE
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45
Ethernet Media Access Controller (ETH)
45.5
Functional Description
Introduction
PIC32CX-BZ6
SoC Family Features
PIC32WM-BZ6
Module Features
1
Acronyms and Abbreviations
2
Ordering Information
3
Configuration Summary
4
PIC32CX-BZ6
SoC Description
5
PIC32WM-BZ6
Module Description
6
Pinout and Signal Descriptions List
7
I/O Ports and Peripheral Pin Select (PPS)
8
Power Subsystem
9
Product Memory Mapping Overview
10
Processor and Architecture
11
Prefetch Cache (PCHE)
12
Cortex M Cache Controller (CMCC)
13
Secure Boot ROM
14
eFuse Controller
15
Security Features
16
Flash Controller (FC)
17
Device Service Unit (DSU)
18
Clock and Reset Unit (CRU)
19
Power Management Unit (PMU)
20
Watchdog Timer (WDT)
21
Deadman Timer (DMT)
22
RAM Error Correction Code (RAMECC)
23
System Configuration and Register Locking (CFG)
24
Peripheral Module Disable (PMD)
25
Peripheral Access Controller (PAC)
26
Real-Time Counter and Calendar (RTCC)
27
Direct Memory Access Controller (DMAC)
28
External Interrupt Controller (EIC)
29
Configurable Custom Logic (CCL)
30
Frequency Meter (FREQM)
31
Event System (EVSYS)
32
Serial Communication Interface (SERCOM)
33
SERCOM Synchronous and Asynchronous Receiver and Transmitter (SERCOM USART)
34
SERCOM Serial Peripheral Interface (SERCOM SPI)
35
SERCOM Inter-Integrated Circuit (SERCOM I
2
C)
36
Quad Serial Peripheral Interface (QSPI)
37
Analog-to-Digital Converter (ADC)
38
Automated Touch Sensing using the Enhance Capacitive Voltage Divider (CVD)
39
Analog Comparators (AC)
40
Digital-to-Analog Converter (DAC)
41
Timer/Counter (TC)
42
Timer/Counter for Control Applications (TCC)
43
Controller Area Network (CAN)
44
Universal Serial Bus (USB)
45
Ethernet Media Access Controller (ETH)
45.1
Overview
45.2
Features
45.3
Block Diagram
45.4
Signal Interface
45.5
Functional Description
45.5.1
Media Access Controller
45.5.2
IEEE 1588 Time Stamp Unit
45.5.3
AHB Direct Memory Access Interface
45.5.4
MAC Transmit Block
45.5.5
MAC Receive Block
45.5.6
Checksum Offload for IP, TCP and UDP
45.5.7
MAC Filtering Block
45.5.8
Broadcast Address
45.5.9
Hash Addressing
45.5.10
Copy all Frames (Promiscuous Mode)
45.5.11
Disable Copy of Pause Frames
45.5.12
VLAN Support
45.5.13
Wake On LAN Support
45.5.14
IEEE 1588 Support
45.5.15
Time Stamp Unit
45.5.16
MAC 802.3 Pause Frame Support
45.5.17
MAC PFC Priority-based Pause Frame Support
45.5.18
Energy Efficient Ethernet Support
45.5.19
LPI Operation in the EMAC
45.5.20
PHY Interface
45.5.21
Jumbo Frames
45.6
Programming Interface
45.7
Register Summary
46
Quadrature Encoder Interface (QEI)
47
Low-Cost Controllerless (LCC)
48
802.15.4 Bluetooth® Radio Subsystem
49
Electrical Characteristics
50
Packaging Information
51
Appendix A: Regulatory Approval
52
Appendix B: Acronyms and Abbreviations
53
Document Revision History
Microchip Information
45.5 Functional Description
