16.2 Features

Flash Controller

  1. PB-Bridge-D Interface that Provides Access to the Flash Controller Registers
  2. AHB Initiator for Bus Hosted Reads the Row Programming Data from SRAM
  3. Write Protect for Program Flash (PFM)
    1. Single page protection resolution
    2. Protect < Address
    3. Protect ≥ Address
  4. Individual Page Write Protection for Boot Flash (BFM)
  5. Error Correction Code Support
  6. Supports Chip and Page Erase
  7. Supports Double Word, Quad Double Word and Row Program Options
  8. Supports Flash Erase/Retry to Increase Retention and Endurance

Flash Memory

  1. 256-Bit Wide Flash Memory Access
  2. 4 Kbytes Page Size
  3. Row Size is 1 KB (256 Word)
  4. Flash-Based One-Time-Programmable (OTP) Page. The Flash controller allows the Flash memory to be accessed through the following methods:
    1. Run-Time Self-Programming (RTSP)
    2. Serial Wire Debug (SWD) programming using DSU
  5. Flash Word is 256 Bits