9.6 SRAM Memory Configuration

Retention

Depending on the application and power budget needs, part of the system memory can be retained in the Deep Sleep mode. The amount of the SRAM retained in this mode is software selectable, by writing the WCMSIZ register in the PMU module, up to 64 KB of SRAM.

By default, no retention is selected.

RAM Error Correction

For safety applications, the PIC32CX-BZ6 family embeds Error Correction Codes (ECC) to detect and correct single bit errors or to enable dual error detection for the system memory. The ECC is software selectable through the CFGCON0.FRECCDIS bit in the boot Flash device configuration. By default, ECC is disabled.

ECC can be applied only for 256 KB of SRAM. When enabled, half the memory will be reserved to store the ECC, and will not be available for the application.

Therefore, when ECC is enabled, usable System RAM is 256 KB (512 KB/2) for the main 512K data RAM variant. Row E is used as ECC memory, if enabled. ECC support for row AL/AU/B/C/D can be selected using the WCMSIZ.SRAM1_SIZ bits and CFGCON0.FRECCDIS. bit.

ECC (Error Correcting Code) is activated when both WCMSIZ.SRAM1SIZ bits are set to ‘0’ and the CFGCON0.FRECCDIS bit is ‘0’. This configuration does not enable Embedded Trace Buffer (ETB) Coresight, but it does support memory rows AL/AU/B/C/D. It is important to note that enabling ECC is independent of the ETB Coresight status. ECC can be utilized across these rows provided that the system has 224 KB of available memory and the 32 KB ETB Coresight feature is enabled. However, ECC should only be enabled if the application is not using the Memory Retention feature during Deep Sleep, which corresponds to WCMSIZ.SRAM1SIZ being ‘00’. This ensures that ECC functionality does not interfere with memory retention requirements.

CoreSight ETB Connection

The following figure illustrates an example where both ECC and CoreSight ETB are enabled.