18.5 Interrupts
There are five interrupts in the RDC/CIC module:
- CICIPDIF interrupt is triggered when input sample processing is done.
- CICOSRIF interrupt is triggered when the output sample is ready.
- CICERRIF interrupt is triggered when
one of the following error conditions occurs:
- A new sample is written into
CICxDOUT before the previous sample has been read (CICOUTOVF(CICSTAT[18]) =
1). - A CIC timeout error has
occurred (FILTOERR(CICSTAT[19]) =
1). - An invalid input error has
occurred (IISERR(CICSTAT[20]) =
1).
- A new sample is written into
CICxDOUT before the previous sample has been read (CICOUTOVF(CICSTAT[18]) =
- RDCCORIF interrupt is triggered when CORDIC block operation is completed.
- RDCERRIF interrupt is triggered when a CIC input channel receives a new sample from its ADC channel before the other CIC input channel has received its prior sample.