14.4.12 CAN Transmit Attempt Interrupt Status Register
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxTXATIFT: Accesses the top byte TXATIF[31:24]
- CxTXATIFU: Accesses the upper byte TXATIF[23:16]
- CxTXATIF: Accesses the byte TXATIF[31:0]
- TFATIFx mirrors the transmit attempt interrupt bit of its respective FIFO register, individual flags need to be cleared in said FIFO register.
| Name: | C1TXATIF |
| Offset: | 0x262C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TFATIF[31:24] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TFATIF[23:16] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TFATIF[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TFATIF[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – TFATIF[31:0] Transmit FIFO/TXQ Attempt Interrup Pending bits
| Value | Description |
|---|---|
| 1 | Interrupt is pending. |
| 0 | Interrupt is not pending. |